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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
Andreas Hansson ccfdc533b9 stats: Bump stats to match DRAM controller changes 
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
2013-11-01 11:56:34 -04:00

1769 lines
200 KiB
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---------- Begin Simulation Statistics ----------
sim_seconds 1.842698 # Number of seconds simulated
sim_ticks 1842698476000 # Number of ticks simulated
final_tick 1842698476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 222585 # Simulator instruction rate (inst/s)
host_op_rate 222585 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5605413242 # Simulator tick rate (ticks/s)
host_mem_usage 334468 # Number of bytes of host memory used
host_seconds 328.74 # Real time elapsed on the host
sim_insts 73171582 # Number of instructions simulated
sim_ops 73171582 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 489344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 20103680 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 144384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 2235712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 284736 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2526400 # Number of bytes read from this memory
system.physmem.bytes_read::total 28436608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 489344 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 144384 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 284736 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 918464 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7460736 # Number of bytes written to this memory
system.physmem.bytes_written::total 7460736 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 7646 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 314120 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2256 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 34933 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 4449 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 39475 # Number of read requests responded to by this memory
system.physmem.num_reads::total 444322 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 116574 # Number of write requests responded to by this memory
system.physmem.num_writes::total 116574 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 265558 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 10909913 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 78355 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1213282 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 154521 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 1371033 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15432046 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 265558 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 78355 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 154521 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 498434 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4048810 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4048810 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4048810 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 265558 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 10909913 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 78355 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1213282 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 154521 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1371033 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19480856 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 98004 # Number of read requests accepted
system.physmem.writeReqs 44399 # Number of write requests accepted
system.physmem.readBursts 98004 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 44399 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 6271808 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
system.physmem.bytesWritten 2840768 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 6272256 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 2841536 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 6232 # Per bank write bursts
system.physmem.perBankRdBursts::1 6028 # Per bank write bursts
system.physmem.perBankRdBursts::2 6221 # Per bank write bursts
system.physmem.perBankRdBursts::3 6513 # Per bank write bursts
system.physmem.perBankRdBursts::4 5794 # Per bank write bursts
system.physmem.perBankRdBursts::5 6242 # Per bank write bursts
system.physmem.perBankRdBursts::6 5925 # Per bank write bursts
system.physmem.perBankRdBursts::7 6039 # Per bank write bursts
system.physmem.perBankRdBursts::8 6348 # Per bank write bursts
system.physmem.perBankRdBursts::9 6026 # Per bank write bursts
system.physmem.perBankRdBursts::10 6373 # Per bank write bursts
system.physmem.perBankRdBursts::11 5867 # Per bank write bursts
system.physmem.perBankRdBursts::12 5876 # Per bank write bursts
system.physmem.perBankRdBursts::13 6234 # Per bank write bursts
system.physmem.perBankRdBursts::14 6235 # Per bank write bursts
system.physmem.perBankRdBursts::15 6044 # Per bank write bursts
system.physmem.perBankWrBursts::0 2859 # Per bank write bursts
system.physmem.perBankWrBursts::1 2656 # Per bank write bursts
system.physmem.perBankWrBursts::2 2839 # Per bank write bursts
system.physmem.perBankWrBursts::3 3122 # Per bank write bursts
system.physmem.perBankWrBursts::4 2688 # Per bank write bursts
system.physmem.perBankWrBursts::5 2969 # Per bank write bursts
system.physmem.perBankWrBursts::6 2850 # Per bank write bursts
system.physmem.perBankWrBursts::7 2699 # Per bank write bursts
system.physmem.perBankWrBursts::8 3075 # Per bank write bursts
system.physmem.perBankWrBursts::9 2558 # Per bank write bursts
system.physmem.perBankWrBursts::10 2888 # Per bank write bursts
system.physmem.perBankWrBursts::11 2432 # Per bank write bursts
system.physmem.perBankWrBursts::12 2458 # Per bank write bursts
system.physmem.perBankWrBursts::13 2707 # Per bank write bursts
system.physmem.perBankWrBursts::14 2844 # Per bank write bursts
system.physmem.perBankWrBursts::15 2743 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
system.physmem.totGap 1841686150500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 98004 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 44399 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 66399 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 14093 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6916 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2029 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 978 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 963 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 570 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 565 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 560 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 617 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 551 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 532 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 457 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 399 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 395 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 394 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 394 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 393 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 395 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 395 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1797 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1789 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1781 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2074 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2372 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 2089 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 2082 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 2113 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 2142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1848 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1844 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 2173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 2221 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 2213 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2232 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 1848 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 1846 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 1797 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 1867 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 1920 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 68 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 17930 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 508.141439 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 169.008973 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1572.275953 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67 7528 41.99% 41.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131 2973 16.58% 58.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195 1838 10.25% 68.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259 1006 5.61% 74.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323 670 3.74% 78.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387 572 3.19% 81.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451 359 2.00% 83.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515 327 1.82% 85.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579 240 1.34% 86.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643 222 1.24% 87.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707 225 1.25% 89.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771 213 1.19% 90.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835 93 0.52% 90.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899 79 0.44% 91.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963 78 0.44% 91.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027 102 0.57% 92.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091 45 0.25% 92.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155 56 0.31% 92.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219 39 0.22% 92.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283 53 0.30% 93.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347 30 0.17% 93.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411 119 0.66% 94.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475 70 0.39% 94.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539 89 0.50% 94.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603 16 0.09% 95.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667 17 0.09% 95.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731 5 0.03% 95.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795 36 0.20% 95.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859 6 0.03% 95.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923 15 0.08% 95.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987 5 0.03% 95.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051 15 0.08% 95.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115 11 0.06% 95.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179 11 0.06% 95.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243 2 0.01% 95.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307 23 0.13% 95.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371 1 0.01% 95.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435 12 0.07% 95.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499 2 0.01% 95.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563 9 0.05% 96.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691 15 0.08% 96.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755 1 0.01% 96.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819 22 0.12% 96.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883 1 0.01% 96.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947 14 0.08% 96.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011 4 0.02% 96.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075 10 0.06% 96.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139 3 0.02% 96.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203 12 0.07% 96.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267 2 0.01% 96.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331 20 0.11% 96.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459 13 0.07% 96.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523 2 0.01% 96.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587 7 0.04% 96.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715 13 0.07% 96.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843 21 0.12% 96.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971 13 0.07% 96.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035 2 0.01% 96.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099 8 0.04% 97.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163 2 0.01% 97.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227 14 0.08% 97.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355 23 0.13% 97.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419 1 0.01% 97.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483 14 0.08% 97.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547 2 0.01% 97.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611 76 0.42% 97.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739 3 0.02% 97.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867 19 0.11% 97.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931 1 0.01% 97.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995 4 0.02% 97.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059 1 0.01% 97.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123 9 0.05% 97.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251 5 0.03% 98.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315 1 0.01% 98.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379 21 0.12% 98.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5507 8 0.04% 98.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635 8 0.04% 98.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699 3 0.02% 98.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763 4 0.02% 98.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891 21 0.12% 98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147 5 0.03% 98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275 5 0.03% 98.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403 19 0.11% 98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531 6 0.03% 98.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595 1 0.01% 98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6659 6 0.03% 98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6787 25 0.14% 98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915 15 0.08% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979 1 0.01% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171 20 0.11% 98.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7491 2 0.01% 98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7683 2 0.01% 98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939 1 0.01% 98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003 2 0.01% 99.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8384-8387 1 0.01% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8451 1 0.01% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8899 2 0.01% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9795 1 0.01% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10051 1 0.01% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10243 1 0.01% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10688-10691 1 0.01% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10880-10883 4 0.02% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11267 1 0.01% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11840-11843 1 0.01% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12035 2 0.01% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12736-12739 1 0.01% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13059 1 0.01% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13120-13123 1 0.01% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13248-13251 2 0.01% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14272-14275 1 0.01% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14400-14403 1 0.01% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14595 1 0.01% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915 1 0.01% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043 1 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363 14 0.08% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15427 1 0.01% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16067 1 0.01% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387 76 0.42% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 17930 # Bytes accessed per row activation
system.physmem.totQLat 2684942500 # Total ticks spent queuing
system.physmem.totMemAccLat 4336678750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 489985000 # Total ticks spent in databus transfers
system.physmem.totBankLat 1161751250 # Total ticks spent accessing banks
system.physmem.avgQLat 27398.21 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 11854.97 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 44253.18 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.18 # Average write queue length when enqueuing
system.physmem.readRowHits 89612 # Number of row buffer hits during reads
system.physmem.writeRowHits 34842 # Number of row buffer hits during writes
system.physmem.readRowHitRate 91.44 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 78.47 # Row buffer hit rate for writes
system.physmem.avgGap 12932916.80 # Average gap between requests
system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 19524796 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 44746 # Transaction distribution
system.membus.trans_dist::ReadResp 44539 # Transaction distribution
system.membus.trans_dist::WriteReq 3750 # Transaction distribution
system.membus.trans_dist::WriteResp 3750 # Transaction distribution
system.membus.trans_dist::Writeback 44399 # Transaction distribution
system.membus.trans_dist::UpgradeReq 43 # Transaction distribution
system.membus.trans_dist::UpgradeResp 43 # Transaction distribution
system.membus.trans_dist::ReadExReq 56527 # Transaction distribution
system.membus.trans_dist::ReadExResp 56527 # Transaction distribution
system.membus.trans_dist::BadAddressError 207 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13312 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189934 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 414 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 203660 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 254372 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15690 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6953984 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 6969674 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 9129482 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 35968328 # Total data (bytes)
system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 12460500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 511769750 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 256500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 762797456 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 153003500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.l2c.tags.replacements 337399 # number of replacements
system.l2c.tags.tagsinuse 65421.710089 # Cycle average of tags in use
system.l2c.tags.total_refs 2471820 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 402562 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 6.140222 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 54901.425298 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 2456.924718 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2698.289857 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 528.309889 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 619.621947 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2142.597203 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 2074.541175 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.837729 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.037490 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.041173 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.008061 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.009455 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.032693 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.031655 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.998256 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 520374 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 492975 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 124091 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 84248 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 292559 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 239147 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1753394 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 835552 # number of Writeback hits
system.l2c.Writeback_hits::total 835552 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 92855 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 26292 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 67775 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 186922 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 520374 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 585830 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu1.data 110540 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu2.data 306922 # number of demand (read+write) hits
system.l2c.demand_hits::total 1940316 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 520374 # number of overall hits
system.l2c.overall_hits::cpu0.data 585830 # number of overall hits
system.l2c.overall_hits::cpu1.inst 124091 # number of overall hits
system.l2c.overall_hits::cpu1.data 110540 # number of overall hits
system.l2c.overall_hits::cpu2.inst 292559 # number of overall hits
system.l2c.overall_hits::cpu2.data 306922 # number of overall hits
system.l2c.overall_hits::total 1940316 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 7646 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 238323 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 2256 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 16912 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 4449 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 18154 # number of ReadReq misses
system.l2c.ReadReq_misses::total 287740 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 10 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 18 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 76073 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 18069 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 21595 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 115737 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 7646 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 314396 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu1.data 34981 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu2.data 39749 # number of demand (read+write) misses
system.l2c.demand_misses::total 403477 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 7646 # number of overall misses
system.l2c.overall_misses::cpu0.data 314396 # number of overall misses
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system.l2c.overall_misses::cpu1.data 34981 # number of overall misses
system.l2c.overall_misses::cpu2.inst 4449 # number of overall misses
system.l2c.overall_misses::cpu2.data 39749 # number of overall misses
system.l2c.overall_misses::total 403477 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst 174436247 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 1133429750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 361724750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 1201174749 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2870765496 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 294997 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 294997 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1255826741 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 1783349726 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 3039176467 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 174436247 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 2389256491 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::cpu2.data 2984524475 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 5909941963 # number of demand (read+write) miss cycles
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system.l2c.overall_miss_latency::cpu1.data 2389256491 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu2.data 2984524475 # number of overall miss cycles
system.l2c.overall_miss_latency::total 5909941963 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 528020 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 731298 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu1.data 101160 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu2.data 257301 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2041134 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 835552 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 835552 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 13 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 25 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 168928 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 44361 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 89370 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 302659 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 528020 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 900226 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu1.data 145521 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu2.data 346671 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2343793 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 528020 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 900226 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu1.data 145521 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu2.data 346671 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2343793 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014481 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.325890 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.017856 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.167181 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.014979 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.070555 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.140971 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.769231 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.720000 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.450328 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.407317 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.241636 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.382401 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014481 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.349241 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu1.data 0.240385 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu2.data 0.114659 # miss rate for demand accesses
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system.l2c.overall_miss_rate::cpu0.inst 0.014481 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.349241 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu2.data 0.114659 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.172147 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77321.031472 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 67019.261471 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 81304.731400 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 66165.844938 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 9976.942712 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 29499.700000 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 16388.722222 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69501.728983 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82581.603427 # average ReadExReq miss latency
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system.l2c.demand_avg_miss_latency::cpu1.data 68301.549155 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 81304.731400 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 75084.265642 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu1.inst 77321.031472 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 68301.549155 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 81304.731400 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 75084.265642 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 14647.531242 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 75062 # number of writebacks
system.l2c.writebacks::total 75062 # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.inst 2256 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 16912 # number of ReadReq MSHR misses
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system.l2c.ReadReq_mshr_misses::cpu2.data 18154 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 41771 # number of ReadReq MSHR misses
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system.l2c.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses
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system.l2c.ReadExReq_mshr_misses::total 39664 # number of ReadExReq MSHR misses
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system.l2c.demand_mshr_misses::cpu1.data 34981 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 4449 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 39749 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 81435 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2256 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 34981 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 4449 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 39749 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 81435 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 146027753 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 921761250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 305687750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 999134251 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 2372611004 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 259007 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 259007 # number of UpgradeReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1518288274 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 2547839033 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 146027753 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1951312009 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 305687750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 2517422525 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 4920450037 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 146027753 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1951312009 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu2.data 2517422525 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 4920450037 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 277798500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 291495500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 569294000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 343775500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 402311000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 746086500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 621574000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 693806500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 1315380500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.167181 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.070555 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.020465 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.769231 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407317 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241636 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.131052 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.240385 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.114659 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.034745 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.240385 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.114659 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.034745 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54503.385170 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 55036.589787 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 56800.435805 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 25900.700000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 25900.700000 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56978.845481 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70307.398657 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 64235.554483 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55782.053372 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63332.977559 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 60421.809259 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55782.053372 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63332.977559 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 60421.809259 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.254914 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1694870261000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.254914 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.078432 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.078432 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
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system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 9304463 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 9304463 # number of ReadReq miss cycles
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system.iocache.WriteReq_miss_latency::total 5314395237 # number of WriteReq miss cycles
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system.iocache.demand_miss_latency::total 5323699700 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 5323699700 # number of overall miss cycles
system.iocache.overall_miss_latency::total 5323699700 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53783.023121 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 53783.023121 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127897.459497 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 127897.459497 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 127590.166567 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 127590.166567 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 127590.166567 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 127590.166567 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 168405 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 12345 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 13.641555 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5715463 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 5715463 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4435167237 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 4435167237 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 4440882700 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 4440882700 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 4440882700 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 4440882700 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82832.797101 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 82832.797101 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262498.060902 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 262498.060902 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 4920992 # DTB read hits
system.cpu0.dtb.read_misses 6099 # DTB read misses
system.cpu0.dtb.read_acv 126 # DTB read access violations
system.cpu0.dtb.read_accesses 428234 # DTB read accesses
system.cpu0.dtb.write_hits 3511178 # DTB write hits
system.cpu0.dtb.write_misses 670 # DTB write misses
system.cpu0.dtb.write_acv 84 # DTB write access violations
system.cpu0.dtb.write_accesses 163777 # DTB write accesses
system.cpu0.dtb.data_hits 8432170 # DTB hits
system.cpu0.dtb.data_misses 6769 # DTB misses
system.cpu0.dtb.data_acv 210 # DTB access violations
system.cpu0.dtb.data_accesses 592011 # DTB accesses
system.cpu0.itb.fetch_hits 2763046 # ITB hits
system.cpu0.itb.fetch_misses 3034 # ITB misses
system.cpu0.itb.fetch_acv 104 # ITB acv
system.cpu0.itb.fetch_accesses 2766080 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 928344318 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 33880492 # Number of instructions committed
system.cpu0.committedOps 33880492 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 31739536 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 169894 # Number of float alu accesses
system.cpu0.num_func_calls 813170 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4699422 # number of instructions that are conditional controls
system.cpu0.num_int_insts 31739536 # number of integer instructions
system.cpu0.num_fp_insts 169894 # number of float instructions
system.cpu0.num_int_register_reads 44596322 # number of times the integer registers were read
system.cpu0.num_int_register_writes 23159667 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 87728 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 89270 # number of times the floating registers were written
system.cpu0.num_mem_refs 8462332 # number of memory refs
system.cpu0.num_load_insts 4942381 # Number of load instructions
system.cpu0.num_store_insts 3519951 # Number of store instructions
system.cpu0.num_idle_cycles 904625586.132235 # Number of idle cycles
system.cpu0.num_busy_cycles 23718731.867765 # Number of busy cycles
system.cpu0.not_idle_fraction 0.025549 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.974451 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6416 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 211386 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 105698 57.89% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1819501633500 98.74% 98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 38918500 0.00% 98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 365019000 0.02% 98.76% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 22792135500 1.24% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1842697706500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.694791 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.815828 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 326 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 192241 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1909
system.cpu0.kern.mode_good::user 1739
system.cpu0.kern.mode_good::idle 170
system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.391309 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 29773270000 1.62% 1.62% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 2593332500 0.14% 1.76% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 1810331099500 98.24% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 4177 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.throughput 110448008 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 784800 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 784578 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 3750 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 3750 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 371852 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 150627 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 133731 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 207 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 846719 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1369630 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 2216349 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27094720 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55304714 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 82399434 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 203511688 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 10688 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 2136322000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 1907046997 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 2233138904 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.iobus.throughput 1469141 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 2975 # Transaction distribution
system.iobus.trans_dist::ReadResp 2975 # Transaction distribution
system.iobus.trans_dist::WriteReq 20646 # Transaction distribution
system.iobus.trans_dist::WriteResp 20646 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8372 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2374 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 13312 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 47242 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4186 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1548 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 15690 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 1098482 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2707184 # Total data (bytes)
system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 6239000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 1789000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 153606200 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 9562000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 17411500 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.icache.tags.replacements 950723 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.190316 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 43428114 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 951234 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 45.654501 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 10399272250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.695807 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.603495 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 159.891014 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.491593 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194538 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.312287 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998419 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 33359431 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 7828902 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2239781 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 43428114 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 33359431 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 7828902 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 2239781 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 43428114 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 33359431 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 7828902 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 2239781 # number of overall hits
system.cpu0.icache.overall_hits::total 43428114 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 528040 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 126347 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 313191 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 967578 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 528040 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 126347 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 313191 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 967578 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 528040 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 126347 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 313191 # number of overall misses
system.cpu0.icache.overall_misses::total 967578 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1802440753 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4440627379 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6243068132 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1802440753 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 4440627379 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6243068132 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1802440753 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 4440627379 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6243068132 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 33887471 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 7955249 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 2552972 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 44395692 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 33887471 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 7955249 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 2552972 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 44395692 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 33887471 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 7955249 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 2552972 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 44395692 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015582 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015882 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122677 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.021794 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015582 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015882 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122677 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.021794 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015582 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015882 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122677 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.021794 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14265.797787 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14178.655769 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 6452.263416 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14265.797787 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14178.655769 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 6452.263416 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14265.797787 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14178.655769 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 6452.263416 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 4969 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 740 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 199 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.969849 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 740 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16174 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 16174 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 16174 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 16174 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 16174 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 16174 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126347 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 297017 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 423364 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 126347 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 297017 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 423364 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 126347 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 297017 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 423364 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1548840247 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3650495745 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5199335992 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1548840247 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3650495745 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 5199335992 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1548840247 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3650495745 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 5199335992 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015882 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116342 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009536 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015882 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116342 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.009536 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015882 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116342 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.009536 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.623054 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12290.527966 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12281.006396 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.623054 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12290.527966 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12281.006396 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.623054 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12290.527966 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12281.006396 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 1391697 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 13286622 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1392209 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 9.543554 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 248.161883 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 130.279675 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 133.556253 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.484691 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.254452 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.260852 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 4083341 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 1084976 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_hits::total 7563969 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3214796 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::cpu2.data 1291573 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5339068 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117279 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19300 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47662 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 184241 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126504 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21337 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51447 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 199288 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 7298137 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 1917675 # number of demand (read+write) hits
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system.cpu0.dcache.demand_hits::total 12903037 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 7298137 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 1917675 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 3687225 # number of overall hits
system.cpu0.dcache.overall_hits::total 12903037 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::cpu2.data 533015 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1353517 # number of ReadReq misses
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system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2165 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6803 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 18759 # number of LoadLockedReq misses
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system.cpu0.dcache.demand_misses::total 2163218 # number of demand (read+write) misses
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system.cpu0.dcache.overall_misses::cpu1.data 143357 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1129415 # number of overall misses
system.cpu0.dcache.overall_misses::total 2163218 # number of overall misses
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system.cpu0.dcache.ReadReq_miss_latency::total 11610367996 # number of ReadReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18147263609 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 19808262368 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28538250 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 102812500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 131350750 # number of LoadLockedReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 3923105759 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_latency::total 31418630364 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 3923105759 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 27495524605 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 31418630364 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 4804848 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1183971 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 2928667 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8917486 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3383735 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 877061 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 1887973 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 6148769 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 127070 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21465 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54465 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 203000 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126504 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21337 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51447 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 199288 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 8188583 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 2061032 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 4816640 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 15066255 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 8188583 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 2061032 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 4816640 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 15066255 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150162 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083613 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181999 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.151782 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049927 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050580 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315894 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.131685 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077052 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100862 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.124906 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092409 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108742 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069556 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234482 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.143580 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108742 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069556 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234482 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.143580 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22850.719733 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17538.457634 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 8577.925505 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37441.926852 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30428.007393 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 24463.675317 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13181.639723 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15112.817874 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7002.012367 # average LoadLockedReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27365.986725 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24344.926006 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14524.024099 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27365.986725 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24344.926006 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14524.024099 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 591087 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 822 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 17697 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33.400407 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 117.428571 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 835552 # number of writebacks
system.cpu0.dcache.writebacks::total 835552 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280898 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 280898 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507265 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 507265 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1373 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1373 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 788163 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 788163 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 788163 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 788163 # number of overall MSHR hits
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system.cpu0.dcache.ReadReq_mshr_misses::total 351112 # number of ReadReq MSHR misses
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system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1563762241 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24206750 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66163500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90370250 # number of LoadLockedReq MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6896212988 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10516080229 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296519000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 310561500 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 364164500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 426924000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 791088500 # number of WriteReq MSHR uncacheable cycles
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system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 737485500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1398169000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083613 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086086 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039373 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050580 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047212 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021711 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100862 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099697 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037414 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069556 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070849 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.032165 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069556 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070849 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.032165 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20769.786353 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16910.272766 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.451318 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35250.039245 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29537.732081 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31435.972269 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11180.946882 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12184.806630 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.650428 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 1203387 # DTB read hits
system.cpu1.dtb.read_misses 1366 # DTB read misses
system.cpu1.dtb.read_acv 34 # DTB read access violations
system.cpu1.dtb.read_accesses 142939 # DTB read accesses
system.cpu1.dtb.write_hits 898859 # DTB write hits
system.cpu1.dtb.write_misses 183 # DTB write misses
system.cpu1.dtb.write_acv 22 # DTB write access violations
system.cpu1.dtb.write_accesses 58529 # DTB write accesses
system.cpu1.dtb.data_hits 2102246 # DTB hits
system.cpu1.dtb.data_misses 1549 # DTB misses
system.cpu1.dtb.data_acv 56 # DTB access violations
system.cpu1.dtb.data_accesses 201468 # DTB accesses
system.cpu1.itb.fetch_hits 859133 # ITB hits
system.cpu1.itb.fetch_misses 692 # ITB misses
system.cpu1.itb.fetch_acv 30 # ITB acv
system.cpu1.itb.fetch_accesses 859825 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 953620014 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 7953643 # Number of instructions committed
system.cpu1.committedOps 7953643 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 7410219 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 45003 # Number of float alu accesses
system.cpu1.num_func_calls 212713 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1020267 # number of instructions that are conditional controls
system.cpu1.num_int_insts 7410219 # number of integer instructions
system.cpu1.num_fp_insts 45003 # number of float instructions
system.cpu1.num_int_register_reads 10384111 # number of times the integer registers were read
system.cpu1.num_int_register_writes 5386902 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 24304 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 24611 # number of times the floating registers were written
system.cpu1.num_mem_refs 2109479 # number of memory refs
system.cpu1.num_load_insts 1208276 # Number of load instructions
system.cpu1.num_store_insts 901203 # Number of store instructions
system.cpu1.num_idle_cycles 922135498.680812 # Number of idle cycles
system.cpu1.num_busy_cycles 31484515.319188 # Number of busy cycles
system.cpu1.not_idle_fraction 0.033016 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.966984 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu1.kern.mode_switch::user 0 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 0
system.cpu1.kern.mode_good::user 0
system.cpu1.kern.mode_good::idle 0
system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
system.cpu2.branchPred.lookups 9128355 # Number of BP lookups
system.cpu2.branchPred.condPredicted 8449925 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 124319 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 7461780 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 6520544 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 87.385905 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 281902 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 13317 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
system.cpu2.dtb.read_hits 3185589 # DTB read hits
system.cpu2.dtb.read_misses 11798 # DTB read misses
system.cpu2.dtb.read_acv 121 # DTB read access violations
system.cpu2.dtb.read_accesses 217406 # DTB read accesses
system.cpu2.dtb.write_hits 2009886 # DTB write hits
system.cpu2.dtb.write_misses 2608 # DTB write misses
system.cpu2.dtb.write_acv 106 # DTB write access violations
system.cpu2.dtb.write_accesses 82301 # DTB write accesses
system.cpu2.dtb.data_hits 5195475 # DTB hits
system.cpu2.dtb.data_misses 14406 # DTB misses
system.cpu2.dtb.data_acv 227 # DTB access violations
system.cpu2.dtb.data_accesses 299707 # DTB accesses
system.cpu2.itb.fetch_hits 369992 # ITB hits
system.cpu2.itb.fetch_misses 5727 # ITB misses
system.cpu2.itb.fetch_acv 273 # ITB acv
system.cpu2.itb.fetch_accesses 375719 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.write_acv 0 # DTB write access violations
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.data_hits 0 # DTB hits
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.numCycles 31308710 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 8320877 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 36988805 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 9128355 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 6802446 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 8846835 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 603748 # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles 9639992 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 11047 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 1973 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 63718 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 87241 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 2552980 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 86276 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 27364450 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.351710 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.294118 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 18517615 67.67% 67.67% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 268760 0.98% 68.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 429758 1.57% 70.22% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 4997201 18.26% 88.48% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 759565 2.78% 91.26% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 164512 0.60% 91.86% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 190396 0.70% 92.56% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 427414 1.56% 94.12% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 1609229 5.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 27364450 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.291560 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.181422 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 8471005 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 9721532 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 8236973 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 308822 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 380199 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 165870 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 12770 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 36596033 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 40157 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 380199 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 8829996 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 2781091 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 5750095 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 8109315 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 1267845 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 35455371 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 2432 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 230458 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents 443882 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands 23756988 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 44373855 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 44317462 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 52634 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 21971271 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 1785717 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 500561 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 59005 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 3706520 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 3341982 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 2099682 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 368903 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 258103 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 32963824 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 619272 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 32519364 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 32677 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 2138512 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 1074729 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 437003 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 27364450 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.188380 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.575952 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 15094542 55.16% 55.16% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 3058510 11.18% 66.34% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 1555503 5.68% 72.02% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 5825063 21.29% 93.31% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 904805 3.31% 96.62% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 480018 1.75% 98.37% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 285628 1.04% 99.41% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 141467 0.52% 99.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 18914 0.07% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 27364450 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 33388 13.55% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 112327 45.58% 59.13% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 100703 40.87% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 26855600 82.58% 82.59% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 20032 0.06% 82.65% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.65% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 8424 0.03% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 3311528 10.18% 92.87% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 2031960 6.25% 99.11% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 288160 0.89% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 32519364 # Type of FU issued
system.cpu2.iq.rate 1.038668 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 246418 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.007578 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 92448223 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 35610975 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 32122316 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 234050 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 114559 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 110669 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 32641435 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 121907 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 186593 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 407978 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 1104 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 4025 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 156833 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 4157 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 26970 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 380199 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 2010765 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 204147 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 34852291 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 222063 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 3341982 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 2099682 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 549953 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 141753 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 1988 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 4025 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 63582 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 127875 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 191457 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 32361861 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 3205658 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 157503 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 1269195 # number of nop insts executed
system.cpu2.iew.exec_refs 5222587 # number of memory reference insts executed
system.cpu2.iew.exec_branches 7560841 # Number of branches executed
system.cpu2.iew.exec_stores 2016929 # Number of stores executed
system.cpu2.iew.exec_rate 1.033638 # Inst execution rate
system.cpu2.iew.wb_sent 32266608 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 32232985 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 18776213 # num instructions producing a value
system.cpu2.iew.wb_consumers 21965918 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 1.029521 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.854788 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 2305690 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 182269 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 176747 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 26984251 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.204438 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.848007 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 16102351 59.67% 59.67% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 2321930 8.60% 68.28% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1225737 4.54% 72.82% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 5569081 20.64% 93.46% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 502606 1.86% 95.32% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 185666 0.69% 96.01% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 176683 0.65% 96.66% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 180209 0.67% 97.33% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 719988 2.67% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 26984251 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 32500866 # Number of instructions committed
system.cpu2.commit.committedOps 32500866 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 4876853 # Number of memory references committed
system.cpu2.commit.loads 2934004 # Number of loads committed
system.cpu2.commit.membars 63840 # Number of memory barriers committed
system.cpu2.commit.branches 7415854 # Number of branches committed
system.cpu2.commit.fp_insts 109494 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 31057555 # Number of committed integer instructions.
system.cpu2.commit.function_calls 228510 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 719988 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 60996891 # The number of ROB reads
system.cpu2.rob.rob_writes 69992925 # The number of ROB writes
system.cpu2.timesIdled 244953 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 3944260 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 1746464525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 31337447 # Number of Instructions Simulated
system.cpu2.committedOps 31337447 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 31337447 # Number of Instructions Simulated
system.cpu2.cpi 0.999083 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 0.999083 # CPI: Total CPI of All Threads
system.cpu2.ipc 1.000918 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 1.000918 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 42570866 # number of integer regfile reads
system.cpu2.int_regfile_writes 22648106 # number of integer regfile writes
system.cpu2.fp_regfile_reads 67644 # number of floating regfile reads
system.cpu2.fp_regfile_writes 67951 # number of floating regfile writes
system.cpu2.misc_regfile_reads 5345306 # number of misc regfile reads
system.cpu2.misc_regfile_writes 257045 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu2.kern.mode_switch::user 0 # number of protection mode switches
system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu2.kern.mode_good::kernel 0
system.cpu2.kern.mode_good::user 0
system.cpu2.kern.mode_good::idle 0
system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu2.kern.swap_context 0 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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