49d88f08b0
This patch changes the default parameter value of conf_table_reported to match the common case. It also simplifies the regression and config scripts to reflect this change.
98 lines
4.1 KiB
Python
98 lines
4.1 KiB
Python
# Copyright (c) 2012 Mark D. Hill and David A. Wood
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nilay Vaish
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import m5, os, optparse, sys
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from m5.objects import *
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m5.util.addToPath('../configs/common')
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from Benchmarks import SysConfig
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import FSConfig
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m5.util.addToPath('../configs/ruby')
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m5.util.addToPath('../configs/topologies')
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import Ruby
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import Options
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# Add the ruby specific and protocol specific options
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Ruby.define_options(parser)
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(options, args) = parser.parse_args()
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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options.l1d_size="32kB"
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options.l1i_size="32kB"
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options.l2_size="4MB"
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options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.num_cpus = 2
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#the system
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mdesc = SysConfig(disk = 'linux-x86.img')
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system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
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mdesc=mdesc, Ruby=True)
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# Dummy voltage domain for all our clock domains
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system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
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system.clk_domain = SrcClockDomain(clock = '1GHz',
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voltage_domain = system.voltage_domain)
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system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
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voltage_domain = system.voltage_domain)
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system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
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for i in xrange(options.num_cpus)]
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Ruby.create_system(options, system, system.piobus, system._dma_ports)
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# Create a seperate clock domain for Ruby
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system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = system.voltage_domain)
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for (i, cpu) in enumerate(system.cpu):
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# create the interrupt controller
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cpu.createInterruptController()
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# Tie the cpu ports to the correct ruby system ports
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cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
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cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
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cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
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cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
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cpu.interrupts.pio = system.piobus.master
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cpu.interrupts.int_master = system.piobus.slave
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cpu.interrupts.int_slave = system.piobus.master
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# Set access_phys_mem to True for ruby port
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system.ruby._cpu_ruby_ports[i].access_phys_mem = True
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system.physmem = [DDR3_1600_x64(range = r)
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for r in system.mem_ranges]
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for i in xrange(len(system.physmem)):
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system.physmem[i].port = system.piobus.master
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root = Root(full_system = True, system = system)
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m5.ticks.setGlobalFrequency('1THz')
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