36f43ff6a5
configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore
--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
421 lines
14 KiB
C++
421 lines
14 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#include "arch/sparc/regfile.hh"
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#include "cpu/thread_context.hh"
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class Checkpoint;
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using namespace SparcISA;
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using namespace std;
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//RegFile class methods
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Addr RegFile::readPC()
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{
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return pc;
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}
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void RegFile::setPC(Addr val)
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{
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pc = val;
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}
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Addr RegFile::readNextPC()
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{
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return npc;
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}
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void RegFile::setNextPC(Addr val)
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{
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npc = val;
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}
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Addr RegFile::readNextNPC()
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{
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return nnpc;
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}
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void RegFile::setNextNPC(Addr val)
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{
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nnpc = val;
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}
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void RegFile::clear()
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{
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floatRegFile.clear();
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intRegFile.clear();
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miscRegFile.clear();
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}
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MiscReg RegFile::readMiscReg(int miscReg)
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{
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return miscRegFile.readReg(miscReg);
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}
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MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc)
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{
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return miscRegFile.readRegWithEffect(miscReg, tc);
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}
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void RegFile::setMiscReg(int miscReg, const MiscReg &val)
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{
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miscRegFile.setReg(miscReg, val);
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}
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void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
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ThreadContext * tc)
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{
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miscRegFile.setRegWithEffect(miscReg, val, tc);
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}
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FloatReg RegFile::readFloatReg(int floatReg, int width)
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{
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return floatRegFile.readReg(floatReg, width);
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}
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FloatReg RegFile::readFloatReg(int floatReg)
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{
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//Use the "natural" width of a single float
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return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
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}
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FloatRegBits RegFile::readFloatRegBits(int floatReg, int width)
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{
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return floatRegFile.readRegBits(floatReg, width);
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}
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FloatRegBits RegFile::readFloatRegBits(int floatReg)
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{
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//Use the "natural" width of a single float
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return floatRegFile.readRegBits(floatReg,
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FloatRegFile::SingleWidth);
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}
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void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
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{
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floatRegFile.setReg(floatReg, val, width);
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}
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void RegFile::setFloatReg(int floatReg, const FloatReg &val)
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{
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//Use the "natural" width of a single float
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setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
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}
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void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
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{
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floatRegFile.setRegBits(floatReg, val, width);
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}
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void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
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{
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//Use the "natural" width of a single float
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floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth);
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}
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IntReg RegFile::readIntReg(int intReg)
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{
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return intRegFile.readReg(intReg);
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}
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void RegFile::setIntReg(int intReg, const IntReg &val)
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{
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intRegFile.setReg(intReg, val);
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}
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int SparcISA::flattenIntIndex(ThreadContext * tc, int reg)
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{
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int gl = tc->readMiscReg(MISCREG_GL);
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int cwp = tc->readMiscReg(MISCREG_CWP);
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//DPRINTF(Sparc, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
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int newReg;
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//The total number of global registers
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int numGlobals = (MaxGL + 1) * 8;
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if(reg < 8)
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{
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//Global register
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//Put it in the appropriate set of globals
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newReg = reg + gl * 8;
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}
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else if(reg < NumIntArchRegs)
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{
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//Regular windowed register
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//Put it in the window pointed to by cwp
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newReg = numGlobals +
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((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
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}
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else if(reg < NumIntArchRegs + NumMicroIntRegs)
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{
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//Microcode register
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//Displace from the end of the regular registers
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newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
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}
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else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
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{
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reg -= (NumIntArchRegs + NumMicroIntRegs);
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if(reg < 8)
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{
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//Global register from the next window
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//Put it in the appropriate set of globals
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newReg = reg + gl * 8;
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}
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else
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{
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//Windowed register from the previous window
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//Put it in the window before the one pointed to by cwp
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newReg = numGlobals +
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((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
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}
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}
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else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
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{
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reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
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if(reg < 8)
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{
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//Global register from the previous window
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//Put it in the appropriate set of globals
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newReg = reg + gl * 8;
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}
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else
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{
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//Windowed register from the next window
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//Put it in the window after the one pointed to by cwp
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newReg = numGlobals +
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((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
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}
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}
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else
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panic("Tried to flatten invalid register index %d!\n", reg);
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DPRINTF(Sparc, "Flattened register %d to %d.\n", reg, newReg);
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return newReg;
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//return intRegFile.flattenIndex(reg);
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}
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void RegFile::serialize(std::ostream &os)
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{
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intRegFile.serialize(os);
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floatRegFile.serialize(os);
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miscRegFile.serialize(os);
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SERIALIZE_SCALAR(pc);
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SERIALIZE_SCALAR(npc);
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SERIALIZE_SCALAR(nnpc);
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}
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void RegFile::unserialize(Checkpoint *cp, const std::string §ion)
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{
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intRegFile.unserialize(cp, section);
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floatRegFile.unserialize(cp, section);
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miscRegFile.unserialize(cp, section);
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UNSERIALIZE_SCALAR(pc);
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UNSERIALIZE_SCALAR(npc);
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UNSERIALIZE_SCALAR(nnpc);
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}
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void RegFile::changeContext(RegContextParam param, RegContextVal val)
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{
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switch(param)
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{
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case CONTEXT_CWP:
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intRegFile.setCWP(val);
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break;
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case CONTEXT_GLOBALS:
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intRegFile.setGlobals(val);
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break;
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default:
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panic("Tried to set illegal context parameter in the SPARC regfile.\n");
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}
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}
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void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
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{
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uint8_t tl = src->readMiscReg(MISCREG_TL);
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// Read all the trap level dependent registers and save them off
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for(int i = 1; i <= MaxTL; i++)
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{
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src->setMiscReg(MISCREG_TL, i);
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dest->setMiscReg(MISCREG_TL, i);
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dest->setMiscReg(MISCREG_TT, src->readMiscReg(MISCREG_TT));
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dest->setMiscReg(MISCREG_TPC, src->readMiscReg(MISCREG_TPC));
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dest->setMiscReg(MISCREG_TNPC, src->readMiscReg(MISCREG_TNPC));
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dest->setMiscReg(MISCREG_TSTATE, src->readMiscReg(MISCREG_TSTATE));
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}
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// Save off the traplevel
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dest->setMiscReg(MISCREG_TL, tl);
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src->setMiscReg(MISCREG_TL, tl);
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// ASRs
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// dest->setMiscReg(MISCREG_Y, src->readMiscReg(MISCREG_Y));
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// dest->setMiscReg(MISCREG_CCR, src->readMiscReg(MISCREG_CCR));
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dest->setMiscReg(MISCREG_ASI, src->readMiscReg(MISCREG_ASI));
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dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK));
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dest->setMiscReg(MISCREG_FPRS, src->readMiscReg(MISCREG_FPRS));
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dest->setMiscReg(MISCREG_SOFTINT, src->readMiscReg(MISCREG_SOFTINT));
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dest->setMiscReg(MISCREG_TICK_CMPR, src->readMiscReg(MISCREG_TICK_CMPR));
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dest->setMiscReg(MISCREG_STICK, src->readMiscReg(MISCREG_STICK));
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dest->setMiscReg(MISCREG_STICK_CMPR, src->readMiscReg(MISCREG_STICK_CMPR));
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// Priv Registers
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dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK));
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dest->setMiscReg(MISCREG_TBA, src->readMiscReg(MISCREG_TBA));
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dest->setMiscReg(MISCREG_PSTATE, src->readMiscReg(MISCREG_PSTATE));
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dest->setMiscReg(MISCREG_PIL, src->readMiscReg(MISCREG_PIL));
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dest->setMiscReg(MISCREG_CWP, src->readMiscReg(MISCREG_CWP));
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// dest->setMiscReg(MISCREG_CANSAVE, src->readMiscReg(MISCREG_CANSAVE));
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// dest->setMiscReg(MISCREG_CANRESTORE, src->readMiscReg(MISCREG_CANRESTORE));
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// dest->setMiscReg(MISCREG_OTHERWIN, src->readMiscReg(MISCREG_OTHERWIN));
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// dest->setMiscReg(MISCREG_CLEANWIN, src->readMiscReg(MISCREG_CLEANWIN));
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// dest->setMiscReg(MISCREG_WSTATE, src->readMiscReg(MISCREG_WSTATE));
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dest->setMiscReg(MISCREG_GL, src->readMiscReg(MISCREG_GL));
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// Hyperprivilged registers
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dest->setMiscReg(MISCREG_HPSTATE, src->readMiscReg(MISCREG_HPSTATE));
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dest->setMiscReg(MISCREG_HINTP, src->readMiscReg(MISCREG_HINTP));
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dest->setMiscReg(MISCREG_HTBA, src->readMiscReg(MISCREG_HTBA));
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dest->setMiscReg(MISCREG_STRAND_STS_REG,
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src->readMiscReg(MISCREG_STRAND_STS_REG));
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dest->setMiscReg(MISCREG_HSTICK_CMPR,
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src->readMiscReg(MISCREG_HSTICK_CMPR));
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// FSR
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dest->setMiscReg(MISCREG_FSR, src->readMiscReg(MISCREG_FSR));
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//Strand Status Register
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dest->setMiscReg(MISCREG_STRAND_STS_REG,
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src->readMiscReg(MISCREG_STRAND_STS_REG));
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// MMU Registers
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dest->setMiscReg(MISCREG_MMU_P_CONTEXT,
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src->readMiscReg(MISCREG_MMU_P_CONTEXT));
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dest->setMiscReg(MISCREG_MMU_S_CONTEXT,
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src->readMiscReg(MISCREG_MMU_S_CONTEXT));
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dest->setMiscReg(MISCREG_MMU_PART_ID,
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src->readMiscReg(MISCREG_MMU_PART_ID));
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dest->setMiscReg(MISCREG_MMU_LSU_CTRL,
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src->readMiscReg(MISCREG_MMU_LSU_CTRL));
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dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0,
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src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0));
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dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1,
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src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1));
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dest->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG,
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src->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG));
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dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0,
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src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0));
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dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1,
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src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1));
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dest->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG,
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src->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
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dest->setMiscReg(MISCREG_MMU_ITLB_SFSR,
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src->readMiscReg(MISCREG_MMU_ITLB_SFSR));
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dest->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS,
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src->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS));
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dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0,
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src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0));
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dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1,
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src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1));
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dest->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG,
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src->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG));
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dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0,
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src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0));
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dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1,
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src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1));
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dest->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG,
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src->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
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dest->setMiscReg(MISCREG_MMU_DTLB_SFSR,
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src->readMiscReg(MISCREG_MMU_DTLB_SFSR));
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dest->setMiscReg(MISCREG_MMU_DTLB_SFAR,
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src->readMiscReg(MISCREG_MMU_DTLB_SFAR));
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dest->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
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src->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS));
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// Scratchpad Registers
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dest->setMiscReg(MISCREG_SCRATCHPAD_R0,
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src->readMiscReg(MISCREG_SCRATCHPAD_R0));
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dest->setMiscReg(MISCREG_SCRATCHPAD_R1,
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src->readMiscReg(MISCREG_SCRATCHPAD_R1));
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dest->setMiscReg(MISCREG_SCRATCHPAD_R2,
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src->readMiscReg(MISCREG_SCRATCHPAD_R2));
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dest->setMiscReg(MISCREG_SCRATCHPAD_R3,
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src->readMiscReg(MISCREG_SCRATCHPAD_R3));
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dest->setMiscReg(MISCREG_SCRATCHPAD_R4,
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src->readMiscReg(MISCREG_SCRATCHPAD_R4));
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dest->setMiscReg(MISCREG_SCRATCHPAD_R5,
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src->readMiscReg(MISCREG_SCRATCHPAD_R5));
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dest->setMiscReg(MISCREG_SCRATCHPAD_R6,
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src->readMiscReg(MISCREG_SCRATCHPAD_R6));
|
|
dest->setMiscReg(MISCREG_SCRATCHPAD_R7,
|
|
src->readMiscReg(MISCREG_SCRATCHPAD_R7));
|
|
|
|
// Queue Registers
|
|
dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD,
|
|
src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD));
|
|
dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL,
|
|
src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL));
|
|
dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD,
|
|
src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD));
|
|
dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL,
|
|
src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL));
|
|
dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD,
|
|
src->readMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD));
|
|
dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL,
|
|
src->readMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL));
|
|
dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD,
|
|
src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD));
|
|
dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL,
|
|
src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL));
|
|
}
|
|
|
|
void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest)
|
|
{
|
|
// First loop through the integer registers.
|
|
for (int i = 0; i < TheISA::NumIntRegs; ++i) {
|
|
dest->setIntReg(i, src->readIntReg(i));
|
|
}
|
|
|
|
// Then loop through the floating point registers.
|
|
for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
|
|
dest->setFloatRegBits(i, src->readFloatRegBits(i));
|
|
}
|
|
|
|
// Copy misc. registers
|
|
copyMiscRegs(src, dest);
|
|
|
|
// Lastly copy PC/NPC
|
|
dest->setPC(src->readPC());
|
|
dest->setNextPC(src->readNextPC());
|
|
dest->setNextNPC(src->readNextNPC());
|
|
}
|