36f43ff6a5
configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore --HG-- extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
307 lines
8.8 KiB
C++
307 lines
8.8 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#include "arch/sparc/asi.hh"
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namespace SparcISA
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{
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bool AsiIsBlock(ASI asi)
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{
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return
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(asi == ASI_BLK_AIUP) ||
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(asi == ASI_BLK_AIUS) ||
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(asi == ASI_BLK_AIUP_L) ||
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(asi == ASI_BLK_AIUS_L) ||
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(asi == ASI_BLK_P) ||
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(asi == ASI_BLK_S) ||
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(asi == ASI_BLK_PL) ||
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(asi == ASI_BLK_SL);
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}
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bool AsiIsPrimary(ASI asi)
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{
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return
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(asi == ASI_AIUP) ||
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(asi == ASI_BLK_AIUP) ||
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(asi == ASI_AIUP_L) ||
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(asi == ASI_BLK_AIUP_L) ||
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(asi == ASI_LDTX_AIUP) ||
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(asi == ASI_LDTX_AIUP_L) ||
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(asi == ASI_P) ||
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(asi == ASI_PNF) ||
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(asi == ASI_PL) ||
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(asi == ASI_PNFL) ||
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(asi == ASI_PST8_P) ||
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(asi == ASI_PST16_P) ||
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(asi == ASI_PST32_P) ||
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(asi == ASI_PST8_PL) ||
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(asi == ASI_PST16_PL) ||
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(asi == ASI_PST32_PL) ||
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(asi == ASI_FL8_P) ||
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(asi == ASI_FL16_P) ||
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(asi == ASI_FL8_PL) ||
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(asi == ASI_FL16_PL) ||
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(asi == ASI_LDTX_P) ||
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(asi == ASI_LDTX_PL) ||
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(asi == ASI_BLK_P) ||
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(asi == ASI_BLK_PL);
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}
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bool AsiIsSecondary(ASI asi)
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{
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return
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(asi == ASI_AIUS) ||
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(asi == ASI_BLK_AIUS) ||
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(asi == ASI_AIUS_L) ||
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(asi == ASI_BLK_AIUS_L) ||
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(asi == ASI_LDTX_AIUS) ||
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(asi == ASI_LDTX_AIUS_L) ||
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(asi == ASI_S) ||
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(asi == ASI_SNF) ||
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(asi == ASI_SL) ||
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(asi == ASI_SNFL) ||
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(asi == ASI_PST8_S) ||
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(asi == ASI_PST16_S) ||
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(asi == ASI_PST32_S) ||
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(asi == ASI_PST8_SL) ||
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(asi == ASI_PST16_SL) ||
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(asi == ASI_PST32_SL) ||
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(asi == ASI_FL8_S) ||
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(asi == ASI_FL16_S) ||
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(asi == ASI_FL8_SL) ||
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(asi == ASI_FL16_SL) ||
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(asi == ASI_LDTX_S) ||
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(asi == ASI_LDTX_SL) ||
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(asi == ASI_BLK_S) ||
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(asi == ASI_BLK_SL);
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}
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bool AsiIsNucleus(ASI asi)
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{
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return
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(asi == ASI_N) ||
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(asi == ASI_NL) ||
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(asi == ASI_LDTX_N) ||
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(asi == ASI_LDTX_NL);
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}
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bool AsiIsAsIfUser(ASI asi)
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{
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return
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(asi == ASI_AIUP) ||
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(asi == ASI_AIUS) ||
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(asi == ASI_BLK_AIUP) ||
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(asi == ASI_BLK_AIUS) ||
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(asi == ASI_AIUP_L) ||
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(asi == ASI_AIUS_L) ||
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(asi == ASI_BLK_AIUP_L) ||
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(asi == ASI_BLK_AIUS_L) ||
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(asi == ASI_LDTX_AIUP) ||
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(asi == ASI_LDTX_AIUS) ||
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(asi == ASI_LDTX_AIUP_L) ||
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(asi == ASI_LDTX_AIUS_L);
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}
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bool AsiIsIO(ASI asi)
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{
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return
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(asi == ASI_REAL_IO) ||
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(asi == ASI_REAL_IO_L);
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}
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bool AsiIsReal(ASI asi)
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{
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return
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(asi == ASI_REAL) ||
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(asi == ASI_REAL_IO) ||
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(asi == ASI_REAL_L) ||
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(asi == ASI_REAL_IO_L) ||
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(asi == ASI_LDTX_REAL) ||
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(asi == ASI_LDTX_REAL_L);
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}
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bool AsiIsLittle(ASI asi)
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{
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return
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(asi == ASI_NL) ||
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(asi == ASI_AIUP_L) ||
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(asi == ASI_AIUS_L) ||
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(asi == ASI_REAL_L) ||
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(asi == ASI_REAL_IO_L) ||
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(asi == ASI_BLK_AIUP_L) ||
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(asi == ASI_BLK_AIUS_L) ||
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(asi == ASI_LDTX_AIUP_L) ||
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(asi == ASI_LDTX_AIUS_L) ||
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(asi == ASI_LDTX_REAL_L) ||
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(asi == ASI_LDTX_NL) ||
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(asi == ASI_PL) ||
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(asi == ASI_SL) ||
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(asi == ASI_PNFL) ||
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(asi == ASI_SNFL) ||
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(asi == ASI_PST8_PL) ||
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(asi == ASI_PST8_SL) ||
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(asi == ASI_PST16_PL) ||
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(asi == ASI_PST16_SL) ||
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(asi == ASI_PST32_PL) ||
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(asi == ASI_PST32_SL) ||
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(asi == ASI_FL8_PL) ||
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(asi == ASI_FL8_SL) ||
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(asi == ASI_FL16_PL) ||
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(asi == ASI_FL16_SL) ||
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(asi == ASI_LDTX_PL) ||
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(asi == ASI_LDTX_SL) ||
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(asi == ASI_BLK_PL) ||
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(asi == ASI_BLK_SL) ||
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(asi == ASI_LTX_L);
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}
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bool AsiIsTwin(ASI asi)
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{
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return
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(asi >= ASI_LDTX_AIUP &&
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asi <= ASI_LDTX_N &&
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asi != ASI_QUEUE) ||
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(asi >= ASI_LDTX_AIUP_L &&
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asi <= ASI_LDTX_NL &&
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asi != 0x2D) ||
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asi == ASI_LDTX_P ||
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asi == ASI_LDTX_S ||
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asi == ASI_LDTX_PL ||
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asi == ASI_LDTX_SL;
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}
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bool AsiIsPartialStore(ASI asi)
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{
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return
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(asi == ASI_PST8_P) ||
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(asi == ASI_PST8_S) ||
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(asi == ASI_PST16_P) ||
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(asi == ASI_PST16_S) ||
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(asi == ASI_PST32_P) ||
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(asi == ASI_PST32_S) ||
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(asi == ASI_PST8_PL) ||
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(asi == ASI_PST8_SL) ||
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(asi == ASI_PST16_PL) ||
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(asi == ASI_PST16_SL) ||
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(asi == ASI_PST32_PL) ||
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(asi == ASI_PST32_SL);
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}
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bool AsiIsFloatingLoad(ASI asi)
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{
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return
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(asi == ASI_FL8_P) ||
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(asi == ASI_FL8_S) ||
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(asi == ASI_FL16_P) ||
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(asi == ASI_FL16_S) ||
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(asi == ASI_FL8_PL) ||
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(asi == ASI_FL8_SL) ||
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(asi == ASI_FL16_PL) ||
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(asi == ASI_FL16_SL);
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}
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bool AsiIsNoFault(ASI asi)
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{
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return
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(asi == ASI_PNF) ||
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(asi == ASI_SNF) ||
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(asi == ASI_PNFL) ||
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(asi == ASI_SNFL);
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}
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bool AsiIsScratchPad(ASI asi)
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{
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return
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(asi == ASI_SCRATCHPAD) ||
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(asi == ASI_HYP_SCRATCHPAD);
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}
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bool AsiIsCmt(ASI asi)
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{
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return
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(asi == ASI_CMT_PER_STRAND);
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}
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bool AsiIsQueue(ASI asi)
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{
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return asi == ASI_QUEUE;
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}
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bool AsiIsInterrupt(ASI asi)
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{
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return asi == ASI_SWVR_INTR_RECEIVE ||
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asi == ASI_SWVR_UDB_INTR_W ||
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asi == ASI_SWVR_UDB_INTR_R ;
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}
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bool AsiIsMmu(ASI asi)
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{
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return asi == ASI_MMU ||
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asi == ASI_LSU_CONTROL_REG ||
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(asi >= ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 &&
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asi <= ASI_IMMU_CTXT_ZERO_CONFIG) ||
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(asi >= ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 &&
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asi <= ASI_IMMU_CTXT_NONZERO_CONFIG) ||
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(asi >= ASI_IMMU &&
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asi <= ASI_IMMU_TSB_PS1_PTR_REG) ||
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(asi >= ASI_ITLB_DATA_IN_REG &&
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asi <= ASI_TLB_INVALIDATE_ALL);
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}
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bool AsiIsUnPriv(ASI asi)
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{
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return asi >= 0x80;
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}
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bool AsiIsPriv(ASI asi)
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{
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return asi <= 0x2f;
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}
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bool AsiIsHPriv(ASI asi)
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{
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return asi >= 0x30 && asi <= 0x7f;
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}
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bool AsiIsReg(ASI asi)
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{
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return AsiIsMmu(asi) || AsiIsScratchPad(asi) ||
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AsiIsSparcError(asi) || AsiIsInterrupt(asi);
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}
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bool AsiIsSparcError(ASI asi)
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{
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return asi == ASI_SPARC_ERROR_EN_REG ||
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asi == ASI_SPARC_ERROR_STATUS_REG;
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}
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}
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