1532 lines
178 KiB
Text
1532 lines
178 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.865012 # Number of seconds simulated
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sim_ticks 1865011607500 # Number of ticks simulated
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final_tick 1865011607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 239114 # Simulator instruction rate (inst/s)
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host_op_rate 239113 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 8418978943 # Simulator tick rate (ticks/s)
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host_mem_usage 338260 # Number of bytes of host memory used
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host_seconds 221.52 # Real time elapsed on the host
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sim_insts 52969539 # Number of instructions simulated
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sim_ops 52969539 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu.inst 962688 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24879872 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 25843520 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 962688 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 962688 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7514368 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7514368 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 15042 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 388748 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 403805 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 117412 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 117412 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 516183 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 13340331 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 13857029 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 516183 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 516183 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4029127 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4029127 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4029127 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 516183 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 13340331 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17886156 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 403805 # Number of read requests accepted
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system.physmem.writeReqs 117412 # Number of write requests accepted
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system.physmem.readBursts 403805 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 117412 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 25836672 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7513280 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 25843520 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7514368 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 25445 # Per bank write bursts
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system.physmem.perBankRdBursts::1 25617 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25496 # Per bank write bursts
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system.physmem.perBankRdBursts::3 25620 # Per bank write bursts
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system.physmem.perBankRdBursts::4 25117 # Per bank write bursts
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system.physmem.perBankRdBursts::5 25178 # Per bank write bursts
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system.physmem.perBankRdBursts::6 24740 # Per bank write bursts
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system.physmem.perBankRdBursts::7 24558 # Per bank write bursts
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system.physmem.perBankRdBursts::8 25032 # Per bank write bursts
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system.physmem.perBankRdBursts::9 25302 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25290 # Per bank write bursts
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system.physmem.perBankRdBursts::11 25006 # Per bank write bursts
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system.physmem.perBankRdBursts::12 24377 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25425 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25800 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25695 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7802 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7592 # Per bank write bursts
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system.physmem.perBankWrBursts::2 7774 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7602 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7239 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7182 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6741 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6416 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7149 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6926 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7200 # Per bank write bursts
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system.physmem.perBankWrBursts::11 7003 # Per bank write bursts
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system.physmem.perBankWrBursts::12 6957 # Per bank write bursts
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system.physmem.perBankWrBursts::13 7880 # Per bank write bursts
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system.physmem.perBankWrBursts::14 8017 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7915 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 50 # Number of times write queue was full causing retry
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system.physmem.totGap 1865006319500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 403805 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 117412 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 314207 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 36490 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 28744 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 24151 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1450 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2607 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 3214 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4203 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5585 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 6297 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 7150 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 8264 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 6799 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 7310 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 7943 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 7596 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 6918 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 6963 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 7091 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5971 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 6192 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 746 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 330 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 325 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 301 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 287 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 308 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 376 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 400 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 341 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::47 298 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 305 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 280 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 268 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 305 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 166 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::59 312 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::60 254 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 168 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 103 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 61234 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 544.625012 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 334.721385 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 417.137572 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 13321 21.75% 21.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 10685 17.45% 39.20% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 4509 7.36% 46.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 2718 4.44% 51.01% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2169 3.54% 54.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1832 2.99% 57.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1887 3.08% 60.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1551 2.53% 63.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 22562 36.85% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 61234 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 78.280396 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 2939.585639 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-8191 5154 99.94% 99.94% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 22.764204 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 18.942160 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::stdev 24.363230 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::16-23 4631 89.80% 89.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-31 32 0.62% 90.42% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-39 183 3.55% 93.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-47 6 0.12% 94.09% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-55 4 0.08% 94.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-63 9 0.17% 94.34% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-71 9 0.17% 94.51% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-79 4 0.08% 94.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-87 32 0.62% 95.21% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-95 5 0.10% 95.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-103 155 3.01% 98.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-111 14 0.27% 98.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-119 9 0.17% 98.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-127 2 0.04% 98.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-135 9 0.17% 98.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-143 4 0.08% 99.05% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-159 1 0.02% 99.07% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-167 2 0.04% 99.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::168-175 8 0.16% 99.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-183 6 0.12% 99.38% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::184-191 10 0.19% 99.57% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-199 10 0.19% 99.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::200-207 1 0.02% 99.79% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-215 1 0.02% 99.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::216-223 4 0.08% 99.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::248-255 1 0.02% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::264-271 2 0.04% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads
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|
system.physmem.totQLat 7801574500 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 15370912000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2018490000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 19325.27 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 38075.27 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 4.03 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.14 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.96 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.64 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 364428 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 95430 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 90.27 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 81.28 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3578176.31 # Average gap between requests
|
|
system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 214821180 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 114180165 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1440644940 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 304576560 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 3637439520.000001 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 4203799590 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 238276320 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.actPowerDownEnergy 7970182890 # Energy for active power-down per rank (pJ)
|
|
system.physmem_0.prePowerDownEnergy 4260887040 # Energy for precharge power-down per rank (pJ)
|
|
system.physmem_0.selfRefreshEnergy 438967517640 # Energy for self refresh per rank (pJ)
|
|
system.physmem_0.totalEnergy 461353182075 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 247.372821 # Core power per rank (mW)
|
|
system.physmem_0.totalIdleTime 1855132089750 # Total Idle time Per DRAM Rank
|
|
system.physmem_0.memoryStateTime::IDLE 377139000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 1545232000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::SREF 1826595828250 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 11096155750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 7918821750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 17478430750 # Time in different power states
|
|
system.physmem_1.actEnergy 222396720 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 118202865 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1441758780 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 308225340 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 3641127360.000001 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 4165097730 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 227687040 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.actPowerDownEnergy 8135120370 # Energy for active power-down per rank (pJ)
|
|
system.physmem_1.prePowerDownEnergy 4246672320 # Energy for precharge power-down per rank (pJ)
|
|
system.physmem_1.selfRefreshEnergy 438904577085 # Energy for self refresh per rank (pJ)
|
|
system.physmem_1.totalEnergy 461412058890 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 247.404390 # Core power per rank (mW)
|
|
system.physmem_1.totalIdleTime 1855277049250 # Total Idle time Per DRAM Rank
|
|
system.physmem_1.memoryStateTime::IDLE 349511250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1546624000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::SREF 1826382821500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 11059060000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 7833171250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 17840419500 # Time in different power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.bridge.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.branchPred.lookups 19540652 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 16609155 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 593501 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 12781935 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 5419166 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 42.397071 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 1123794 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 42287 # Number of incorrect RAS predictions.
|
|
system.cpu.branchPred.indirectLookups 6265125 # Number of indirect predictor lookups.
|
|
system.cpu.branchPred.indirectHits 563559 # Number of indirect target hits.
|
|
system.cpu.branchPred.indirectMisses 5701566 # Number of indirect misses.
|
|
system.cpu.branchPredindirectMispredicted 264926 # Number of mispredicted indirect branches.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 11133148 # DTB read hits
|
|
system.cpu.dtb.read_misses 49550 # DTB read misses
|
|
system.cpu.dtb.read_acv 604 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 995639 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6779390 # DTB write hits
|
|
system.cpu.dtb.write_misses 12217 # DTB write misses
|
|
system.cpu.dtb.write_acv 419 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 345330 # DTB write accesses
|
|
system.cpu.dtb.data_hits 17912538 # DTB hits
|
|
system.cpu.dtb.data_misses 61767 # DTB misses
|
|
system.cpu.dtb.data_acv 1023 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1340969 # DTB accesses
|
|
system.cpu.itb.fetch_hits 1814760 # ITB hits
|
|
system.cpu.itb.fetch_misses 10379 # ITB misses
|
|
system.cpu.itb.fetch_acv 753 # ITB acv
|
|
system.cpu.itb.fetch_accesses 1825139 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numPwrStateTransitions 12878 # Number of power state transitions
|
|
system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::mean 279577818.217114 # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::stdev 438970116.286468 # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::min_value 62000 # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateResidencyTicks::ON 64810036000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.pwrStateResidencyTicks::CLK_GATED 1800201571500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.numCycles 129626512 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 30190363 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 85695972 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 19540652 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 7106519 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 91835709 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1682318 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 61 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.MiscStallCycles 29737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 207098 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 428060 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 576 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 9928105 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 408572 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 123532763 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.693710 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.023135 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 107696719 87.18% 87.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 1032377 0.84% 88.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 2107068 1.71% 89.72% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 968796 0.78% 90.51% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2908740 2.35% 92.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 664008 0.54% 93.40% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 809572 0.66% 94.05% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1033225 0.84% 94.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 6312258 5.11% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 123532763 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.150746 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.661099 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 24222797 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 86210181 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 10254650 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 2038697 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 806437 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 738100 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 35530 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 74041720 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 113425 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 806437 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 25231796 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 56630169 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 20045874 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 11215615 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 9602870 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 71021126 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 199714 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2114917 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 266619 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 5298821 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 47846131 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 85558708 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 85377795 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 168460 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 38170817 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 9675306 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1730146 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 277278 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 13907871 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 11664536 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 7226725 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1727084 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1123210 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 62712842 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2208202 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 60540114 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 93631 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 11951500 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 5299174 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1546957 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 123532763 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.490073 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.235792 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 98992964 80.13% 80.13% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 10407106 8.42% 88.56% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 4428528 3.58% 92.14% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 3186499 2.58% 94.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 3245157 2.63% 97.35% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 1605158 1.30% 98.65% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1098083 0.89% 99.54% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 432605 0.35% 99.89% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 136663 0.11% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 123532763 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 207032 16.63% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 1 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 606591 48.74% 65.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 372500 29.93% 95.30% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMemRead 31949 2.57% 97.87% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMemWrite 26498 2.13% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 7276 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 40915146 67.58% 67.60% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 62152 0.10% 67.70% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 38560 0.06% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 11521390 19.03% 86.80% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 6745321 11.14% 97.94% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMemRead 156180 0.26% 98.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMemWrite 141327 0.23% 98.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 949126 1.57% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 60540114 # Type of FU issued
|
|
system.cpu.iq.rate 0.467035 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 1244571 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.020558 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 245211528 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 76534751 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 58316055 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 739664 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 359442 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 336937 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 61379259 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 398150 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 691177 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 2573780 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 3893 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 22128 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 849514 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 18020 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 462679 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 806437 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 52697038 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1357053 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 68903527 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 198807 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 11664536 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 7226725 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1959166 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 45872 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 1108146 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 22128 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 230653 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 630212 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 860865 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 59685899 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 11215511 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 854214 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 3982483 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 18027322 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 9384105 # Number of branches executed
|
|
system.cpu.iew.exec_stores 6811811 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.460445 # Inst execution rate
|
|
system.cpu.iew.wb_sent 58897557 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 58652992 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 29769052 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 41264413 # num instructions consuming a value
|
|
system.cpu.iew.wb_rate 0.452477 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.721422 # average fanout of values written-back
|
|
system.cpu.commit.commitSquashedInsts 12552458 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 661245 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 769809 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 121361631 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.462746 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.395074 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 101505032 83.64% 83.64% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 7973925 6.57% 90.21% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4190958 3.45% 93.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2263923 1.87% 95.53% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1758393 1.45% 96.98% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 630847 0.52% 97.50% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 481222 0.40% 97.89% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 521755 0.43% 98.32% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 2035576 1.68% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 121361631 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 56159642 # Number of instructions committed
|
|
system.cpu.commit.committedOps 56159642 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 15467967 # Number of memory references committed
|
|
system.cpu.commit.loads 9090756 # Number of loads committed
|
|
system.cpu.commit.membars 226364 # Number of memory barriers committed
|
|
system.cpu.commit.branches 8439956 # Number of branches committed
|
|
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 52009640 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 740476 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 3197376 5.69% 5.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 36210459 64.48% 70.17% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 60672 0.11% 70.28% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 9172524 16.33% 86.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 6245101 11.12% 97.81% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 949126 1.69% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 56159642 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 2035576 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 187788618 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 139599579 # The number of ROB writes
|
|
system.cpu.timesIdled 556181 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 6093749 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 3600396704 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 52969539 # Number of Instructions Simulated
|
|
system.cpu.committedOps 52969539 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 2.447190 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.447190 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.408632 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.408632 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 77875050 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 42594378 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 166655 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 175866 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 2002132 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 939499 # number of misc regfile writes
|
|
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.tags.replacements 1405977 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.994060 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 12626898 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1406489 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 8.977602 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 28232500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.994060 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 67141007 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 67141007 # Number of data accesses
|
|
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 8018368 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 8018368 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4180367 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4180367 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 212226 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 212226 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 215667 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 215667 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 12198735 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 12198735 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 12198735 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 12198735 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1817070 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1817070 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1966374 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1966374 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 23459 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 23459 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 98 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 98 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3783444 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3783444 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3783444 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3783444 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 45126424500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 45126424500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 92431305073 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 92431305073 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 416761500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 416761500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1368500 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 1368500 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 137557729573 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 137557729573 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 137557729573 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 137557729573 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 9835438 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 9835438 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6146741 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6146741 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235685 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 235685 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 215765 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 215765 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 15982179 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15982179 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 15982179 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15982179 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184747 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.184747 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319905 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.319905 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099535 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099535 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000454 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000454 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.236729 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.236729 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.236729 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.236729 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24834.719906 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 24834.719906 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47005.963806 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 47005.963806 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17765.527090 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17765.527090 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13964.285714 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13964.285714 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36357.807747 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 36357.807747 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36357.807747 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 36357.807747 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 4938618 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 4294 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 133157 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.088685 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 153.357143 # average number of cycles each access was blocked
|
|
system.cpu.dcache.writebacks::writebacks 844399 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 844399 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716933 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 716933 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676859 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1676859 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6505 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 6505 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2393792 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 2393792 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2393792 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 2393792 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100137 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1100137 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289515 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 289515 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16954 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 16954 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 98 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 98 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1389652 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1389652 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1389652 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1389652 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33017901000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33017901000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14364764991 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 14364764991 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 212848500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 212848500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1270500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1270500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47382665991 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 47382665991 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47382665991 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 47382665991 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535128000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535128000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535128000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535128000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111854 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111854 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047101 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047101 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071935 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071935 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000454 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000454 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086950 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.086950 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086950 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.086950 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30012.535711 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30012.535711 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49616.651956 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49616.651956 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12554.470921 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12554.470921 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12964.285714 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12964.285714 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34096.785376 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34096.785376 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34096.785376 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34096.785376 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221519.191919 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221519.191919 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92874.826063 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92874.826063 # average overall mshr uncacheable latency
|
|
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.tags.replacements 1076759 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 509.003606 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 8782144 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1077267 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 8.152245 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 30283847500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 509.003606 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.994148 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.994148 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 11005677 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 11005677 # Number of data accesses
|
|
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 8782144 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 8782144 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 8782144 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 8782144 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 8782144 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 8782144 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1145952 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1145952 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1145952 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1145952 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1145952 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1145952 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16332614990 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 16332614990 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 16332614990 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 16332614990 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 16332614990 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 16332614990 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 9928096 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 9928096 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 9928096 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 9928096 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 9928096 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 9928096 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115425 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.115425 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.115425 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.115425 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.115425 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.115425 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14252.442502 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 14252.442502 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14252.442502 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 14252.442502 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14252.442502 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 14252.442502 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 8348 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 326 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 25.607362 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.writebacks::writebacks 1076759 # number of writebacks
|
|
system.cpu.icache.writebacks::total 1076759 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68371 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 68371 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 68371 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 68371 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 68371 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 68371 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077581 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1077581 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1077581 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1077581 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1077581 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1077581 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14423902993 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 14423902993 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14423902993 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 14423902993 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14423902993 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 14423902993 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108539 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.108539 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.108539 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13385.446656 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13385.446656 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13385.446656 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 13385.446656 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13385.446656 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 13385.446656 # average overall mshr miss latency
|
|
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.tags.replacements 338614 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65420.353665 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 4559964 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 404136 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 11.283241 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 6414398000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 255.266765 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 5296.205124 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 59868.881776 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.003895 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080814 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.913527 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.998235 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5602 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58570 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 40121077 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 40121077 # Number of data accesses
|
|
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 844399 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 844399 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 1076079 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 1076079 # number of WritebackClean hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 69 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 69 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 98 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 98 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 185276 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 185276 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1062141 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 1062141 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 832063 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 832063 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1062141 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1017339 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2079480 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1062141 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1017339 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2079480 # number of overall hits
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 114725 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 114725 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15044 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 15044 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274467 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 274467 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 15044 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 389192 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 404236 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 15044 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 389192 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 404236 # number of overall misses
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 418500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 418500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12044968500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 12044968500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1516847000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 1516847000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22392456000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 22392456000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1516847000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 34437424500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 35954271500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1516847000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 34437424500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 35954271500 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 844399 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 844399 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 1076079 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 1076079 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 78 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 98 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 98 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 300001 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 300001 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1077185 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 1077185 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106530 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 1106530 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1077185 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1406531 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2483716 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1077185 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1406531 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2483716 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.115385 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.115385 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382415 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.382415 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013966 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013966 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248043 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248043 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013966 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.276703 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.162755 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013966 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.276703 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.162755 # miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 46500 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 46500 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104989.919372 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104989.919372 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 100827.373039 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 100827.373039 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81585.239756 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81585.239756 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 100827.373039 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88484.410008 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 88943.764286 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 100827.373039 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88484.410008 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 88943.764286 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.writebacks::writebacks 75900 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 75900 # number of writebacks
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114725 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 114725 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15043 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15043 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274467 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274467 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15043 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 389192 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 404235 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15043 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 389192 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 404235 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 328500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 328500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10897718500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10897718500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1366325500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1366325500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19653014500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19653014500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1366325500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30550733000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 31917058500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1366325500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30550733000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 31917058500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448486500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448486500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448486500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448486500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.115385 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382415 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382415 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013965 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248043 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248043 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276703 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.162754 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276703 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.162754 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 36500 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36500 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94989.919372 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94989.919372 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90827.993086 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90827.993086 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71604.289405 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71604.289405 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90827.993086 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78497.844252 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78956.692271 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90827.993086 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78497.844252 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78956.692271 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209016.810967 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209016.810967 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87633.038901 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87633.038901 # average overall mshr uncacheable latency
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 4967024 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483092 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2362 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 951 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 951 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2191157 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 920299 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 1076759 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 824292 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 78 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 98 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 176 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 300001 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 300001 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1077581 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106690 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::BadAddressError 40 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::InvalidateReq 237 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3231525 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252605 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 7484130 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137852416 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144111100 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 281963516 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 339563 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoopTraffic 4892928 # Total snoop traffic (bytes)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 2839828 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.001278 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.035720 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 2836200 99.87% 99.87% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 3628 0.13% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 2839828 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 4417734000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1617399440 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2121770107 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51151 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 51151 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 33058 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 116508 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20216 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 5359000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 14034000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 2179500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 6056500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 92500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 216222032 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.iocache.tags.replacements 41685 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.265413 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1714256790000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.079088 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375525 # Number of data accesses
|
|
system.iocache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
|
system.iocache.overall_misses::total 41725 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 21932883 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 21932883 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::tsunami.ide 4939835149 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 4939835149 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 4961768032 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 4961768032 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 4961768032 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 4961768032 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126779.670520 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 126779.670520 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118883.210170 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 118883.210170 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 118915.950437 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 118915.950437 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 118915.950437 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 118915.950437 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 2115 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 16 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 132.187500 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
|
system.iocache.writebacks::total 41512 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13282883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 13282883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2859804565 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 2859804565 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 2873087448 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 2873087448 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 2873087448 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 2873087448 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76779.670520 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 76779.670520 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68824.715176 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.715176 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.697975 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 68857.697975 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.697975 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 68857.697975 # average overall mshr miss latency
|
|
system.membus.snoop_filter.tot_requests 825525 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 380458 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 414 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadReq 6930 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 296573 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 9599 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 9599 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 117412 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 262094 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 137 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 114597 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 114597 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 289683 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 40 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145815 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 80 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178953 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1262378 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30700160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30744316 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 33402044 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 438 # Total snoops (count)
|
|
system.membus.snoopTraffic 27840 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 462498 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0.001464 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0.038232 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 461821 99.85% 99.85% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 462498 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 28738500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1313413567 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 48500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2137867250 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 917617 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 211030 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 105578 57.93% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 182260 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1819136783500 97.54% 97.54% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 67099500 0.00% 97.54% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 565538000 0.03% 97.57% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 45241360000 2.43% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1865010781000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.694302 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::total 0.815418 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175141 91.22% 93.43% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 191988 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1908
|
|
system.cpu.kern.mode_good::user 1738
|
|
system.cpu.kern.mode_good::idle 170
|
|
system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 29668657000 1.59% 1.59% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 2761122500 0.15% 1.74% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1832580993500 98.26% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
|
|
|
|
---------- End Simulation Statistics ----------
|