5b08e211ab
Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
1058 lines
120 KiB
Text
1058 lines
120 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.064767 # Number of seconds simulated
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sim_ticks 64766858000 # Number of ticks simulated
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final_tick 64766858000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 139181 # Simulator instruction rate (inst/s)
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host_op_rate 177937 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 33015138 # Simulator tick rate (ticks/s)
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host_mem_usage 270440 # Number of bytes of host memory used
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host_seconds 1961.73 # Real time elapsed on the host
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sim_insts 273036725 # Number of instructions simulated
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sim_ops 349064449 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 194688 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 272960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 467648 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 194688 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 194688 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3042 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 4265 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 7307 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 3005982 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 4214501 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 7220483 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 3005982 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 3005982 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 3005982 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4214501 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 7220483 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 7307 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 7307 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 467648 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 467648 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 604 # Per bank write bursts
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system.physmem.perBankRdBursts::1 805 # Per bank write bursts
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system.physmem.perBankRdBursts::2 608 # Per bank write bursts
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system.physmem.perBankRdBursts::3 526 # Per bank write bursts
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system.physmem.perBankRdBursts::4 446 # Per bank write bursts
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system.physmem.perBankRdBursts::5 361 # Per bank write bursts
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system.physmem.perBankRdBursts::6 162 # Per bank write bursts
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system.physmem.perBankRdBursts::7 221 # Per bank write bursts
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system.physmem.perBankRdBursts::8 208 # Per bank write bursts
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system.physmem.perBankRdBursts::9 290 # Per bank write bursts
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system.physmem.perBankRdBursts::10 326 # Per bank write bursts
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system.physmem.perBankRdBursts::11 415 # Per bank write bursts
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system.physmem.perBankRdBursts::12 530 # Per bank write bursts
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system.physmem.perBankRdBursts::13 688 # Per bank write bursts
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system.physmem.perBankRdBursts::14 613 # Per bank write bursts
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system.physmem.perBankRdBursts::15 504 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 64766656000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 7307 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 4265 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 2120 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 623 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 69 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1462 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 319.430917 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 186.825713 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 340.055999 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 519 35.50% 35.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 381 26.06% 61.56% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 138 9.44% 71.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 81 5.54% 76.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 49 3.35% 79.89% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 41 2.80% 82.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 27 1.85% 84.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 24 1.64% 86.18% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 202 13.82% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1462 # Bytes accessed per row activation
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system.physmem.totQLat 61897500 # Total ticks spent queuing
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system.physmem.totMemAccLat 198903750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 36535000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 8470.99 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 27220.99 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 7.22 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 7.22 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.06 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 5841 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 79.94 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 8863645.27 # Average gap between requests
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system.physmem.pageHitRate 79.94 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 60826618500 # Time in different power states
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system.physmem.memoryStateTime::REF 2162680000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 1777002750 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.membus.throughput 7220483 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 4488 # Transaction distribution
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system.membus.trans_dist::ReadResp 4488 # Transaction distribution
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system.membus.trans_dist::UpgradeReq 3 # Transaction distribution
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system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
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system.membus.trans_dist::ReadExReq 2819 # Transaction distribution
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system.membus.trans_dist::ReadExResp 2819 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14620 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 14620 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467648 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 467648 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 467648 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 8747000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 67869997 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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|
system.cpu.branchPred.lookups 36489443 # Number of BP lookups
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system.cpu.branchPred.condPredicted 21873029 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 1677086 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 19094793 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 17269038 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 90.438467 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 7051020 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 13969 # Number of incorrect RAS predictions.
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 191 # Number of system calls
|
|
system.cpu.numCycles 129533717 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 40065447 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 327212599 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 36489443 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 24320058 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 72959266 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 8220576 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 9614052 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 38688978 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 553522 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 129167933 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 3.246487 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.483221 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 56843632 44.01% 44.01% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 6961373 5.39% 49.40% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 5946764 4.60% 54.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 6307392 4.88% 58.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 5037669 3.90% 62.78% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 4117601 3.19% 65.97% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 3252291 2.52% 68.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 4297115 3.33% 71.82% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 36404096 28.18% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 129167933 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.281698 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.526081 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 43040295 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 8294549 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 70704377 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 671384 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 6457328 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 7532389 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 70819 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 413867422 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 226829 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 6457328 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 45867800 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 237018 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 350499 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 68547941 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 7707347 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 406294876 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2372159 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 1808118 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 3023073 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.FullRegisterEvents 35743 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 447044512 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 2837901709 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 1622364142 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 210216215 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 62478319 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 12155 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 12154 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 14556867 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 106022236 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 93881214 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 5184446 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 5926802 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 394612578 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 23007 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 378124394 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 2730874 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 45321613 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 166213653 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 887 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 129167933 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.927386 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.138502 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 23289729 18.03% 18.03% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 17219322 13.33% 31.36% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 17000952 13.16% 44.52% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 16863081 13.06% 57.58% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 22471092 17.40% 74.98% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 15547625 12.04% 87.01% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 10749417 8.32% 95.33% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 4018790 3.11% 98.45% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 2007925 1.55% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 129167933 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 70479 0.37% 0.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 4864 0.03% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 116556 0.60% 1.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 10208 0.05% 1.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 2498 0.01% 1.06% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 1.06% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 192000 1.00% 2.06% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 6622 0.03% 2.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 104426 0.54% 2.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 10354293 53.72% 56.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 8412591 43.65% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 127925021 33.83% 33.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 2175908 0.58% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 6 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 6792348 1.80% 36.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 8524841 2.25% 38.46% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 3465145 0.92% 39.37% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1600581 0.42% 39.80% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 21035851 5.56% 45.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 7175261 1.90% 47.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134800 1.89% 49.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.19% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 103072110 27.26% 76.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 89047235 23.55% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 378124394 # Type of FU issued
|
|
system.cpu.iq.rate 2.919119 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 19274540 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.050974 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 653351237 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 300092831 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 252502629 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 254070898 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 139884609 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 118704168 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 266903131 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 130495803 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 12681428 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 11373488 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 85866 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 20564 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 11505631 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 299397 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 2800 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 6457328 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 4758 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 17342 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 394637253 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 715920 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 106022236 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 93881214 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 11972 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 602 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 17793 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 20564 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 1298443 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 381522 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1679965 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 373834206 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 101210545 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 4290188 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1668 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 189079864 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 32211788 # Number of branches executed
|
|
system.cpu.iew.exec_stores 87869319 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.885999 # Inst execution rate
|
|
system.cpu.iew.wb_sent 372104883 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 371206797 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 194146455 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 400678068 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.865716 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.484545 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 45577363 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1607073 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 122710605 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.844620 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.797026 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 31366686 25.56% 25.56% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 25118346 20.47% 46.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 12977285 10.58% 56.61% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 10004590 8.15% 64.76% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 11874018 9.68% 74.44% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 6164142 5.02% 79.46% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 4197962 3.42% 82.88% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 3586787 2.92% 85.80% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 17420789 14.20% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 122710605 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 273037337 # Number of instructions committed
|
|
system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 177024331 # Number of memory references committed
|
|
system.cpu.commit.loads 94648748 # Number of loads committed
|
|
system.cpu.commit.membars 11033 # Number of memory barriers committed
|
|
system.cpu.commit.branches 30563497 # Number of branches committed
|
|
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 279584611 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 6225112 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 116648967 33.42% 33.42% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 2145845 0.61% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 34.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 6594343 1.89% 35.92% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 35.92% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.28% 38.20% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.89% 39.09% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.45% 39.54% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 19652356 5.63% 45.17% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.04% 47.21% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 49.29% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 94648748 27.11% 76.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 82375583 23.60% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 349065061 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 17420789 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 499929717 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 795751266 # The number of ROB writes
|
|
system.cpu.timesIdled 6646 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 365784 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 273036725 # Number of Instructions Simulated
|
|
system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.474419 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.474419 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 2.107843 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 2.107843 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 1785673756 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 235086257 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 188627632 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 133402932 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1210936846 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 21331404 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 17706 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 17706 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1042 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 2839 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 2839 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31825 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10310 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 42135 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1018304 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 363072 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 1381376 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 1381376 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 11837000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 24407489 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 7420712 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 14019 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1852.281625 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 38671572 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 15912 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 2430.340121 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1852.281625 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.904434 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.904434 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1893 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1526 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.924316 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 77393866 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 77393866 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 38671572 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 38671572 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 38671572 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 38671572 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 38671572 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 38671572 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 17404 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 17404 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 17404 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 17404 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 17404 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 17404 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 452089736 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 452089736 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 452089736 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 452089736 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 452089736 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 452089736 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 38688976 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 38688976 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 38688976 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 38688976 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 38688976 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 38688976 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000450 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000450 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000450 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000450 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000450 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000450 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25976.197196 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 25976.197196 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25976.197196 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 25976.197196 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25976.197196 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 25976.197196 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 1041 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 47.318182 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15914 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 15914 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 15914 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 15914 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359079759 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 359079759 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359079759 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 359079759 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359079759 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 359079759 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000411 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000411 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000411 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22563.765175 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22563.765175 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22563.765175 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 22563.765175 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22563.765175 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 22563.765175 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 3952.099762 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 13258 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 5413 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 2.449289 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 379.383220 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2782.580366 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 790.136176 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.011578 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084918 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.024113 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.120609 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5413 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1243 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4021 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165192 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 180948 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 180948 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 12858 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 305 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 13163 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1042 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1042 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 20 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 20 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 12858 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 325 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 13183 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 12858 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 325 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 13183 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3053 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1487 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4540 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 2819 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 2819 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3053 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 4306 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 7359 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3053 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 4306 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 7359 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 214550000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 110145250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 324695250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 200330000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 200330000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 214550000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 310475250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 525025250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 214550000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 310475250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 525025250 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15911 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1792 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 17703 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1042 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1042 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2839 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 2839 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 15911 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4631 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 20542 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 15911 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4631 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 20542 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.191880 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.829799 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.256454 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992955 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992955 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.191880 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.929821 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.358242 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.191880 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.929821 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.358242 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70275.139207 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74072.125084 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71518.777533 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71064.207166 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71064.207166 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70275.139207 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72102.937761 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 71344.646012 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70275.139207 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72102.937761 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 71344.646012 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3042 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1446 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4488 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2819 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 2819 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3042 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 4265 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 7307 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3042 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 4265 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 7307 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175689250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 89225250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264914500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 165556500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 165556500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175689250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254781750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 430471000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175689250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254781750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 430471000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191188 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.806920 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253516 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992955 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992955 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191188 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.920967 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.355710 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191188 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.920967 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.355710 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57754.520053 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61704.875519 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59027.295009 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58728.804541 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58728.804541 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57754.520053 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59737.807737 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58912.139045 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57754.520053 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59737.807737 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58912.139045 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1426 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 3109.599416 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 170089338 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 4631 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 36728.425394 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 3109.599416 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.759180 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.759180 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 3205 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 688 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2446 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.782471 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 340235219 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 340235219 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 88036573 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 88036573 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 82030829 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 82030829 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11027 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 11027 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 170067402 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 170067402 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 170067402 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 170067402 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 4132 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 4132 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 21836 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 21836 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 25968 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 25968 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 25968 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 25968 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 240617705 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 240617705 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1280155018 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 1280155018 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 1520772723 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 1520772723 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 1520772723 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 1520772723 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 88040705 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 88040705 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11029 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 11029 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 170093370 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 170093370 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 170093370 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 170093370 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000266 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000266 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000153 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000153 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000153 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000153 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58232.745644 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 58232.745644 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58625.893845 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 58625.893845 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 58563.336530 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 58563.336530 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 58563.336530 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 58563.336530 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 30153 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 1162 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 553 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.526221 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 96.833333 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1042 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1042 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2339 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 2339 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18995 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 18995 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 21334 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 21334 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 21334 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 21334 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1793 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1793 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 4634 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 4634 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 4634 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 4634 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115097041 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 115097041 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203424247 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 203424247 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 318521288 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 318521288 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318521288 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 318521288 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64192.437814 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64192.437814 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71603.043647 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71603.043647 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68735.711696 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68735.711696 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68735.711696 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68735.711696 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|