gem5/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
Steve Reinhardt 9e45ada171 stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00

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Redirecting stdout to build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest/simerr
M5 Simulator System
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:52:02
M5 executing on zizzer
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 268782974 because maximum number of loads reached