142 lines
4.2 KiB
C++
142 lines
4.2 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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*/
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/* @file
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* User Console Definitions
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*/
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#ifndef __SIM_OBJECT_HH__
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#define __SIM_OBJECT_HH__
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#include <map>
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#include <list>
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#include <vector>
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#include <iostream>
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#include "sim/serialize.hh"
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#include "sim/startup.hh"
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class BaseCPU;
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class Event;
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/*
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* Abstract superclass for simulation objects. Represents things that
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* correspond to physical components and can be specified via the
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* config file (CPUs, caches, etc.).
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*/
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class SimObject : public Serializable, protected StartupCallback
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{
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public:
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struct Params {
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std::string name;
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};
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enum State {
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Running,
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Draining,
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Drained
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};
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enum MemoryMode {
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Invalid=0,
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Atomic,
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Timing
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};
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private:
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State state;
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protected:
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Params *_params;
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void changeState(State new_state) { state = new_state; }
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public:
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const Params *params() const { return _params; }
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State getState() { return state; }
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private:
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typedef std::vector<SimObject *> SimObjectList;
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// list of all instantiated simulation objects
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static SimObjectList simObjectList;
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public:
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SimObject(Params *_params);
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SimObject(const std::string &_name);
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virtual ~SimObject() {}
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virtual const std::string name() const { return params()->name; }
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// initialization pass of all objects.
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// Gets invoked after construction, before unserialize.
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virtual void init();
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static void initAll();
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// register statistics for this object
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virtual void regStats();
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virtual void regFormulas();
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virtual void resetStats();
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// static: call reg_stats on all SimObjects
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static void regAllStats();
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// static: call resetStats on all SimObjects
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static void resetAllStats();
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// static: call nameOut() & serialize() on all SimObjects
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static void serializeAll(std::ostream &);
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static void unserializeAll(Checkpoint *cp);
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// Methods to drain objects in order to take checkpoints
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// Or switch from timing -> atomic memory model
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// Drain returns 0 if the simobject can drain immediately or
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// the number of times the drain_event's process function will be called
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// before the object will be done draining. Normally this should be 1
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virtual unsigned int drain(Event *drain_event);
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virtual void resume();
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virtual void setMemoryMode(State new_mode);
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virtual void switchOut();
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virtual void takeOverFrom(BaseCPU *cpu);
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#ifdef DEBUG
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public:
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bool doDebugBreak;
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static void debugObjectBreak(const std::string &objs);
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#endif
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public:
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void recordEvent(const std::string &stat);
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};
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#endif // __SIM_OBJECT_HH__
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