47ff0af17e
separate the rx thread and tx thread and get rid of the dedicated flag.
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
python/m5/objects/Ethernet.py:
dedicated flag goes away, we have new individual flags for
rx thread and tx thread
dev/sinic.cc:
Virtualize sinic
- The io registers are replicated many times in memory, allowing the NIC to
differentiate among several virtual interfaces.
- On the TX side, this allows multiple CPUs to initiate transmits at the same
time without locking in the software. If a partial packet is transmitted,
then the state machine blocks waiting for that virtual interface to complete
its packet. Then the state machine will move on to the next virtual
interface. The commands are kept in fifo order.
- On the RX side, multiple partial transmits can be simultaneously done.
Though a packet does not deallocate its fifo space until all preceeding
packets in the fifo are deallocated. To enable multiple receives, it
is necessary for each virtual nic to keep its own information about its
progress through the state machine.
dev/sinic.hh:
Virtualize sinic
Receive state must be virtualized since we allow the receipt of packets in
parallel.
dev/sinicreg.hh:
Virtualize sinic
separate rx thread and tx thread
create a soft interrupt and add a command to trigger it.
pad out the reserved bits in the RxDone and TxDone regs
--HG--
extra : convert_revision : c10bb23a46a89ffd1e08866c1f1621cb98069205
217 lines
9.5 KiB
C++
217 lines
9.5 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DEV_SINICREG_HH__
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#define __DEV_SINICREG_HH__
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#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL)
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#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL)
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#define __SINIC_VAL32(NAME, OFFSET, WIDTH) \
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static const uint32_t NAME##_width = WIDTH; \
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static const uint32_t NAME##_offset = OFFSET; \
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static const uint32_t NAME##_mask = (1 << WIDTH) - 1; \
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static const uint32_t NAME = ((1 << WIDTH) - 1) << OFFSET; \
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static inline uint32_t get_##NAME(uint32_t reg) \
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{ return (reg & NAME) >> OFFSET; } \
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static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \
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{ return (reg & ~NAME) | ((val << OFFSET) & NAME); }
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#define __SINIC_VAL64(NAME, OFFSET, WIDTH) \
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static const uint64_t NAME##_width = WIDTH; \
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static const uint64_t NAME##_offset = OFFSET; \
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static const uint64_t NAME##_mask = (ULL(1) << WIDTH) - 1; \
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static const uint64_t NAME = ((ULL(1) << WIDTH) - 1) << OFFSET; \
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static inline uint64_t get_##NAME(uint64_t reg) \
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{ return (reg & NAME) >> OFFSET; } \
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static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
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{ return (reg & ~NAME) | ((val << OFFSET) & NAME); }
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namespace Sinic {
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namespace Regs {
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static const int VirtualMask = 0xff;
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static const int VirtualShift = 8;
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// Registers
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__SINIC_REG32(Config, 0x00); // 32: configuration register
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__SINIC_REG32(Command, 0x04); // 32: command register
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__SINIC_REG32(IntrStatus, 0x08); // 32: interrupt status
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__SINIC_REG32(IntrMask, 0x0c); // 32: interrupt mask
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__SINIC_REG32(RxMaxCopy, 0x10); // 32: max bytes per rx copy
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__SINIC_REG32(TxMaxCopy, 0x14); // 32: max bytes per tx copy
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__SINIC_REG32(RxMaxIntr, 0x18); // 32: max receives per interrupt
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__SINIC_REG32(Reserved0, 0x1c); // 32: reserved
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__SINIC_REG32(RxFifoSize, 0x20); // 32: rx fifo capacity in bytes
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__SINIC_REG32(TxFifoSize, 0x24); // 32: tx fifo capacity in bytes
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__SINIC_REG32(RxFifoMark, 0x28); // 32: rx fifo high watermark
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__SINIC_REG32(TxFifoMark, 0x2c); // 32: tx fifo low watermark
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__SINIC_REG32(RxData, 0x30); // 64: receive data
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__SINIC_REG32(RxDone, 0x38); // 64: receive done
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__SINIC_REG32(RxWait, 0x40); // 64: receive done (busy wait)
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__SINIC_REG32(TxData, 0x48); // 64: transmit data
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__SINIC_REG32(TxDone, 0x50); // 64: transmit done
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__SINIC_REG32(TxWait, 0x58); // 64: transmit done (busy wait)
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__SINIC_REG32(HwAddr, 0x60); // 64: mac address
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__SINIC_REG32(Size, 0x68); // register addres space size
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// Config register bits
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__SINIC_VAL32(Config_RxThread, 9, 1); // enable receive threads
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__SINIC_VAL32(Config_TxThread, 8, 1); // enable transmit thread
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__SINIC_VAL32(Config_Filter, 7, 1); // enable receive filter
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__SINIC_VAL32(Config_Vlan, 6, 1); // enable vlan tagging
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__SINIC_VAL32(Config_Virtual, 5, 1); // enable virtual addressing
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__SINIC_VAL32(Config_Desc, 4, 1); // enable tx/rx descriptors
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__SINIC_VAL32(Config_Poll, 3, 1); // enable polling
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__SINIC_VAL32(Config_IntEn, 2, 1); // enable interrupts
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__SINIC_VAL32(Config_TxEn, 1, 1); // enable transmit
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__SINIC_VAL32(Config_RxEn, 0, 1); // enable receive
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// Command register bits
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__SINIC_VAL32(Command_Intr, 1, 1); // software interrupt
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__SINIC_VAL32(Command_Reset, 0, 1); // reset chip
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// Interrupt register bits
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__SINIC_VAL32(Intr_Soft, 8, 1); // software interrupt
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__SINIC_VAL32(Intr_TxLow, 7, 1); // tx fifo dropped below watermark
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__SINIC_VAL32(Intr_TxFull, 6, 1); // tx fifo full
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__SINIC_VAL32(Intr_TxDMA, 5, 1); // tx dma completed w/ interrupt
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__SINIC_VAL32(Intr_TxPacket, 4, 1); // packet transmitted
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__SINIC_VAL32(Intr_RxHigh, 3, 1); // rx fifo above high watermark
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__SINIC_VAL32(Intr_RxEmpty, 2, 1); // rx fifo empty
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__SINIC_VAL32(Intr_RxDMA, 1, 1); // rx dma completed w/ interrupt
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__SINIC_VAL32(Intr_RxPacket, 0, 1); // packet received
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__SINIC_REG32(Intr_All, 0x01ff); // all valid interrupts
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__SINIC_REG32(Intr_NoDelay, 0x01cc); // interrupts that aren't coalesced
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__SINIC_REG32(Intr_Res, ~0x01ff); // reserved interrupt bits
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// RX Data Description
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__SINIC_VAL64(RxData_Len, 40, 20); // 0 - 1M
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__SINIC_VAL64(RxData_Addr, 0, 40); // Address 1TB
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// TX Data Description
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__SINIC_VAL64(TxData_More, 63, 1); // Packet not complete (will dma more)
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__SINIC_VAL64(TxData_Checksum, 62, 1); // do checksum
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__SINIC_VAL64(TxData_Len, 40, 20); // 0 - 1M
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__SINIC_VAL64(TxData_Addr, 0, 40); // Address 1TB
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// RX Done/Busy Information
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__SINIC_VAL64(RxDone_Packets, 32, 16); // number of packets in rx fifo
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__SINIC_VAL64(RxDone_Busy, 31, 1); // receive dma busy copying
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__SINIC_VAL64(RxDone_Complete, 30, 1); // valid data (packet complete)
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__SINIC_VAL64(RxDone_More, 29, 1); // Packet has more data (dma again)
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__SINIC_VAL64(RxDone_Res0, 28, 1); // reserved
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__SINIC_VAL64(RxDone_Res1, 27, 1); // reserved
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__SINIC_VAL64(RxDone_Res2, 26, 1); // reserved
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__SINIC_VAL64(RxDone_TcpError, 25, 1); // TCP packet error (bad checksum)
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__SINIC_VAL64(RxDone_UdpError, 24, 1); // UDP packet error (bad checksum)
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__SINIC_VAL64(RxDone_IpError, 23, 1); // IP packet error (bad checksum)
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__SINIC_VAL64(RxDone_TcpPacket, 22, 1); // this is a TCP packet
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__SINIC_VAL64(RxDone_UdpPacket, 21, 1); // this is a UDP packet
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__SINIC_VAL64(RxDone_IpPacket, 20, 1); // this is an IP packet
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__SINIC_VAL64(RxDone_CopyLen, 0, 20); // up to 256k
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// TX Done/Busy Information
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__SINIC_VAL64(TxDone_Packets, 32, 16); // number of packets in tx fifo
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__SINIC_VAL64(TxDone_Busy, 31, 1); // transmit dma busy copying
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__SINIC_VAL64(TxDone_Complete, 30, 1); // valid data (packet complete)
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__SINIC_VAL64(TxDone_Full, 29, 1); // tx fifo is full
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__SINIC_VAL64(TxDone_Low, 28, 1); // tx fifo is below the watermark
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__SINIC_VAL64(TxDone_Res0, 27, 1); // reserved
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__SINIC_VAL64(TxDone_Res1, 26, 1); // reserved
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__SINIC_VAL64(TxDone_Res2, 25, 1); // reserved
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__SINIC_VAL64(TxDone_Res3, 24, 1); // reserved
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__SINIC_VAL64(TxDone_Res4, 23, 1); // reserved
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__SINIC_VAL64(TxDone_Res5, 22, 1); // reserved
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__SINIC_VAL64(TxDone_Res6, 21, 1); // reserved
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__SINIC_VAL64(TxDone_Res7, 20, 1); // reserved
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__SINIC_VAL64(TxDone_CopyLen, 0, 20); // up to 256k
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struct Info
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{
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uint8_t size;
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bool read;
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bool write;
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bool delay_read;
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bool delay_write;
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const char *name;
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};
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/* namespace Regs */ }
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inline const Regs::Info&
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regInfo(Addr daddr)
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{
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static Regs::Info invalid = { 0, false, false, false, false, "invalid" };
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static Regs::Info info [] = {
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{ 4, true, true, false, false, "Config" },
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{ 4, false, true, false, false, "Command" },
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{ 4, true, true, false, false, "IntrStatus" },
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{ 4, true, true, false, false, "IntrMask" },
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{ 4, true, false, false, false, "RxMaxCopy" },
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{ 4, true, false, false, false, "TxMaxCopy" },
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{ 4, true, false, false, false, "RxMaxIntr" },
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invalid,
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{ 4, true, false, false, false, "RxFifoSize" },
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{ 4, true, false, false, false, "TxFifoSize" },
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{ 4, true, false, false, false, "RxFifoMark" },
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{ 4, true, false, false, false, "TxFifoMark" },
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{ 8, true, true, false, true, "RxData" },
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invalid,
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{ 8, true, false, false, false, "RxDone" },
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invalid,
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{ 8, true, false, false, false, "RxWait" },
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invalid,
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{ 8, true, true, false, true, "TxData" },
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invalid,
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{ 8, true, false, false, false, "TxDone" },
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invalid,
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{ 8, true, false, false, false, "TxWait" },
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invalid,
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{ 8, true, false, false, false, "HwAddr" },
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invalid,
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};
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return info[daddr / 4];
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}
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inline bool
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regValid(Addr daddr)
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{
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if (daddr > Regs::Size)
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return false;
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if (regInfo(daddr).size == 0)
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return false;
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return true;
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}
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/* namespace Sinic */ }
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#endif // __DEV_SINICREG_HH__
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