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gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
Steve Reinhardt 9d8fec0d90 stats: update stats for mmap() change. 
SE O3 runs see an additional reg read per mmap() call.
2016-03-17 10:25:11 -07:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.000022 # Number of seconds simulated
sim_ticks 21900500 # Number of ticks simulated
final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 27169 # Simulator instruction rate (inst/s)
host_op_rate 27167 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 93368241 # Simulator tick rate (ticks/s)
host_mem_usage 228936 # Number of bytes of host memory used
host_seconds 0.23 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 19840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10944 # Number of bytes read from this memory
system.physmem.bytes_read::total 30784 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19840 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19840 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 310 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 171 # Number of read requests responded to by this memory
system.physmem.num_reads::total 481 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 905915390 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 499714618 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1405630008 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 905915390 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 905915390 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 905915390 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 499714618 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1405630008 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 481 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 481 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 30784 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 30784 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 68 # Per bank write bursts
system.physmem.perBankRdBursts::1 32 # Per bank write bursts
system.physmem.perBankRdBursts::2 32 # Per bank write bursts
system.physmem.perBankRdBursts::3 47 # Per bank write bursts
system.physmem.perBankRdBursts::4 41 # Per bank write bursts
system.physmem.perBankRdBursts::5 20 # Per bank write bursts
system.physmem.perBankRdBursts::6 1 # Per bank write bursts
system.physmem.perBankRdBursts::7 3 # Per bank write bursts
system.physmem.perBankRdBursts::8 0 # Per bank write bursts
system.physmem.perBankRdBursts::9 1 # Per bank write bursts
system.physmem.perBankRdBursts::10 22 # Per bank write bursts
system.physmem.perBankRdBursts::11 25 # Per bank write bursts
system.physmem.perBankRdBursts::12 14 # Per bank write bursts
system.physmem.perBankRdBursts::13 118 # Per bank write bursts
system.physmem.perBankRdBursts::14 45 # Per bank write bursts
system.physmem.perBankRdBursts::15 12 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 21763000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 481 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 337.822785 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 215.071445 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 323.417518 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 22 27.85% 54.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 9 11.39% 65.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 9 11.39% 77.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 4 5.06% 82.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1 1.27% 83.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3 3.80% 87.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation
system.physmem.totQLat 3965000 # Total ticks spent queuing
system.physmem.totMemAccLat 12983750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2405000 # Total ticks spent in databus transfers
system.physmem.avgQLat 8243.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 26993.24 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1405.63 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1405.63 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 10.98 # Data bus utilization in percentage
system.physmem.busUtilRead 10.98 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 387 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 45245.32 # Average gap between requests
system.physmem.pageHitRate 80.46 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1630200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 13775205 # Total energy per rank (pJ)
system.physmem_0.averagePower 870.058740 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 209750 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 317520 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 173250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1287000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 10183905 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 566250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 13545045 # Total energy per rank (pJ)
system.physmem_1.averagePower 855.521554 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 873500 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 14452750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 2551 # Number of BP lookups
system.cpu.branchPred.condPredicted 1518 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 429 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1991 # Number of BTB lookups
system.cpu.branchPred.BTBHits 726 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 36.464088 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 383 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 2033 # DTB read hits
system.cpu.dtb.read_misses 43 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 2076 # DTB read accesses
system.cpu.dtb.write_hits 1052 # DTB write hits
system.cpu.dtb.write_misses 28 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 1080 # DTB write accesses
system.cpu.dtb.data_hits 3085 # DTB hits
system.cpu.dtb.data_misses 71 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 3156 # DTB accesses
system.cpu.itb.fetch_hits 2086 # ITB hits
system.cpu.itb.fetch_misses 32 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2118 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 43802 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 8360 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 14953 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2551 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1109 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 4527 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 940 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 730 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 2086 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 308 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 14111 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.059670 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.447373 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 11381 80.65% 80.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 309 2.19% 82.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 232 1.64% 84.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 210 1.49% 85.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 257 1.82% 87.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 204 1.45% 89.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 249 1.76% 91.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 144 1.02% 92.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1125 7.97% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 14111 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.058239 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.341377 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8350 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 2903 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2283 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 178 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 397 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 199 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 74 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 13658 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 213 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 397 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 8499 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1362 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 551 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2297 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1005 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 13185 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 9916 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 16517 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 16508 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 5346 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 571 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2513 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1264 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 12094 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 10150 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 5749 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3122 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 14111 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.719297 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.444291 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 10252 72.65% 72.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1258 8.92% 81.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 873 6.19% 87.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 669 4.74% 92.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 489 3.47% 95.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 327 2.32% 98.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 176 1.25% 99.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 44 0.31% 99.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 23 0.16% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 14111 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 18 13.64% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.64% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 73 55.30% 68.94% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 41 31.06% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 6822 67.21% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.24% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.26% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2214 21.81% 89.07% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1109 10.93% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 10150 # Type of FU issued
system.cpu.iq.rate 0.231725 # Inst issue rate
system.cpu.iq.fu_busy_cnt 132 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013005 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 34530 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 17879 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 9316 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 10269 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1330 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 399 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 71 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 397 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1267 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 12206 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2513 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1264 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 85 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 341 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 9752 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2076 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 84 # number of nop insts executed
system.cpu.iew.exec_refs 3158 # number of memory reference insts executed
system.cpu.iew.exec_branches 1540 # Number of branches executed
system.cpu.iew.exec_stores 1082 # Number of stores executed
system.cpu.iew.exec_rate 0.222638 # Inst execution rate
system.cpu.iew.wb_sent 9474 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 9326 # cumulative count of insts written-back
system.cpu.iew.wb_producers 4992 # num instructions producing a value
system.cpu.iew.wb_consumers 6833 # num instructions consuming a value
system.cpu.iew.wb_rate 0.212913 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.730572 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 5821 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 356 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 13063 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.489091 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.409393 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 10626 81.34% 81.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1163 8.90% 90.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 487 3.73% 93.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 202 1.55% 95.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 127 0.97% 96.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 82 0.63% 97.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 98 0.75% 97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 84 0.64% 98.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 194 1.49% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 13063 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6389 # Number of instructions committed
system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2048 # Number of memory references committed
system.cpu.commit.loads 1183 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 1050 # Number of branches committed
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
system.cpu.commit.int_insts 6307 # Number of committed integer instructions.
system.cpu.commit.function_calls 127 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
system.cpu.commit.bw_lim_events 194 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 24728 # The number of ROB reads
system.cpu.rob.rob_writes 25475 # The number of ROB writes
system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 29691 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6372 # Number of Instructions Simulated
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 6.874137 # CPI: Cycles Per Instruction
system.cpu.cpi_total 6.874137 # CPI: Total CPI of All Threads
system.cpu.ipc 0.145473 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.145473 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12363 # number of integer regfile reads
system.cpu.int_regfile_writes 7056 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 107.516544 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.309942 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 107.516544 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.026249 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.026249 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 171 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041748 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 5747 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5747 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1770 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1770 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits
system.cpu.dcache.overall_hits::total 2276 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 153 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 153 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses
system.cpu.dcache.overall_misses::total 512 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11315000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11315000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23651475 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 23651475 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 34966475 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 34966475 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 34966475 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 34966475 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1923 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1923 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2788 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2788 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2788 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2788 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::total 73954.248366 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 65881.545961 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 68293.896484 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 68293.896484 # average overall miss latency
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system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 341 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 171 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 171 # number of overall MSHR misses
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 5669500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 14010500 # number of overall MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency
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system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
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system.cpu.icache.ReadReq_misses::total 459 # number of ReadReq misses
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system.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency
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system.cpu.icache.overall_mshr_hits::total 148 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::total 311 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency
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system.cpu.l2cache.tags.tagsinuse 218.211579 # Cycle average of tags in use
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system.cpu.l2cache.tags.sampled_refs 409 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012482 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4337 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4337 # Number of data accesses
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system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses
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system.cpu.l2cache.ReadCleanReq_misses::total 310 # number of ReadCleanReq misses
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system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7195000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7195000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20280000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12033500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 32313500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20280000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12033500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 32313500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996785 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997925 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997925 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67201.388889 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67201.388889 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65419.354839 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65419.354839 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72676.767677 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72676.767677 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 311 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 99 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 622 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 342 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19904 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 466500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 256500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 409 # Transaction distribution
system.membus.trans_dist::ReadExReq 72 # Transaction distribution
system.membus.trans_dist::ReadExResp 72 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 409 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 962 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 962 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30784 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 30784 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 481 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 481 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 481 # Request fanout histogram
system.membus.reqLayer0.occupancy 586000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 2558250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 11.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
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