196 lines
9.6 KiB
C++
196 lines
9.6 KiB
C++
// -*- mode:c++ -*-
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// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
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// This software is part of the M5 simulator.
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// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
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// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
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// TO THESE TERMS AND CONDITIONS.
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// Permission is granted to use, copy, create derivative works and
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// distribute this software and such derivative works for any purpose,
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// so long as (1) the copyright notice above, this grant of permission,
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// and the disclaimer below appear in all copies and derivative works
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// made, (2) the copyright notice above is augmented as appropriate to
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// reflect the addition of any new copyrightable work in a derivative
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// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
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// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
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// advertising or publicity pertaining to the use or distribution of
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// this software without specific, written prior authorization.
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// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
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// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
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// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
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// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
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// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
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// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
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// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
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// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
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// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
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// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
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// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
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//Authors: Korey L. Sewell
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// Jaidev Patwardhan
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def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'sh' : ('signed int', 16),
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'uh' : ('unsigned int', 16),
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'sw' : ('signed int', 32),
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'uw' : ('unsigned int', 32),
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'sd' : ('signed int', 64),
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'ud' : ('unsigned int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64),
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}};
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def operands {{
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#General Purpose Integer Reg Operands
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'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
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'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
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'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
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#Immediate Value operand
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'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
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#Operands used for Link or Syscall Insts
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'R31': ('IntReg', 'uw','31','IsInteger', 4),
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'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
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#Special Integer Reg operands
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'LO0': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 6),
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'HI0': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 7),
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#Bitfield-dependent HI/LO Register Access
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'LO_RD_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACDST*3', None, 6),
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'HI_RD_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACDST*3', None, 7),
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'LO_RS_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACSRC*3', None, 6),
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'HI_RS_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACSRC*3', None, 7),
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#DSP Special Purpose Integer Operands
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'DSPControl': ('IntReg', 'uw', 'MipsISA::DSPControl', None, 8),
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'DSPLo0': ('IntReg', 'uw', 'MipsISA::LO', None, 1),
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'DSPHi0': ('IntReg', 'uw', 'MipsISA::HI', None, 1),
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'DSPACX0': ('IntReg', 'uw', 'MipsISA::DSPACX0', None, 1),
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'DSPLo1': ('IntReg', 'uw', 'MipsISA::DSPLo1', None, 1),
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'DSPHi1': ('IntReg', 'uw', 'MipsISA::DSPHi1', None, 1),
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'DSPACX1': ('IntReg', 'uw', 'MipsISA::DSPACX1', None, 1),
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'DSPLo2': ('IntReg', 'uw', 'MipsISA::DSPLo2', None, 1),
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'DSPHi2': ('IntReg', 'uw', 'MipsISA::DSPHi2', None, 1),
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'DSPACX2': ('IntReg', 'uw', 'MipsISA::DSPACX2', None, 1),
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'DSPLo3': ('IntReg', 'uw', 'MipsISA::DSPLo3', None, 1),
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'DSPHi3': ('IntReg', 'uw', 'MipsISA::DSPHi3', None, 1),
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'DSPACX3': ('IntReg', 'uw', 'MipsISA::DSPACX3', None, 1),
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#Floating Point Reg Operands
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'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
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'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
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'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
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'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
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#Special Purpose Floating Point Control Reg Operands
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'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1),
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'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2),
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'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3),
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'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3),
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'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3),
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#Operands For Paired Singles FP Operations
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'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
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'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
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'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
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'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
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'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
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'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
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'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
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'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
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#Status Control Reg
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'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1),
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#LL Flag
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'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1),
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# Index Register
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'Index':('ControlReg','uw','MipsISA::Index',None,1),
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#Special cases for when a Control Register Access is dependent on
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#a combination of bitfield indices (handles MTCO & MFCO)
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# Fixed to allow CP0 Register Offset
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'CP0_RD_SEL': ('IControlReg', 'uw', '(RD << 3 | SEL) + Ctrl_Base_DepTag', None, 1),
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#MT Control Regs
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'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1),
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'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1),
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'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1),
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'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1),
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'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1),
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'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1),
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'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1),
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'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1),
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#CP0 Control Regs
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'EntryHi': ('ControlReg','uw', 'MipsISA::EntryHi',None,1),
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'EntryLo0': ('ControlReg','uw', 'MipsISA::EntryLo0',None,1),
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'EntryLo1': ('ControlReg','uw', 'MipsISA::EntryLo1',None,1),
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'PageMask': ('ControlReg','uw', 'MipsISA::PageMask',None,1),
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'Random': ('ControlReg','uw', 'MipsISA::CP0_Random',None,1),
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'ErrorEPC': ('ControlReg','uw', 'MipsISA::ErrorEPC',None,1),
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'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1),
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'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1),
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'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1),
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'Config': ('ControlReg','uw', 'MipsISA::Config',None,1),
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'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1),
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'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1),
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'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1),
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'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1),
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# named bitfields of Control Regs
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'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
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'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
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'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
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'Status_BEV': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
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'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
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'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
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'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
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'Status_CU0': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
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'SRSCtl_HSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
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'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
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'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
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'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3),
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'Config_MT': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 1),
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'Config1_CA': ('ControlBitfield', 'uw', 'MipsISA::Config1', None, 1),
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'Config3_SP': ('ControlBitfield', 'uw', 'MipsISA::Config3', None, 1),
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'PageGrain_ESP': ('ControlBitfield', 'uw', 'MipsISA::PageGrain', None, 1),
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'Cause_EXCCODE': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4),
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'Cause_TI': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4),
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'IntCtl_IPTI': ('ControlBitfield', 'uw', 'MipsISA::IntCtl', None, 4),
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'EntryHi_ASID': ('ControlBitfield', 'uw', 'MipsISA::EntryHi', None, 1),
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'EntryLo0_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
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'EntryLo0_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 3),
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'EntryLo0_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
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'EntryLo0_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
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'EntryLo0_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
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'EntryLo1_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
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'EntryLo1_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 3),
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'EntryLo1_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
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'EntryLo1_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
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'EntryLo1_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
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# named bitfields of Debug Regs
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'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1),
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'Debug_IEXI': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1),
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#Memory Operand
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'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
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#Program Counter Operands
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'NPC': ('NPC', 'uw', None, 'IsControl', 4),
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'NNPC':('NNPC', 'uw', None, 'IsControl', 4)
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}};
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