9ce632d1f0
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/platform.cc:
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
Updated copyright
dev/tsunamireg.h:
Updated copyright and fixed a ULL
--HG--
extra : convert_revision : 4800bd227c7064044ee98169d6a91f74c791956f
436 lines
13 KiB
C++
436 lines
13 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Tsunami I/O including PIC, PIT, RTC, DMA
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*/
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#include <sys/time.h>
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "dev/console.hh"
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#include "dev/tlaser_clock.hh"
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#include "dev/tsunami_io.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "dev/tsunami_cchip.hh"
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using namespace std;
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#define UNIX_YEAR_OFFSET 52
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// Timer Event for Periodic interrupt of RTC
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TsunamiIO::RTCEvent::RTCEvent(Tsunami* t)
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: Event(&mainEventQueue), tsunami(t)
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{
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DPRINTF(MC146818, "RTC Event Initilizing\n");
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schedule(curTick + ticksPerSecond/RTC_RATE);
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}
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void
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TsunamiIO::RTCEvent::process()
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{
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DPRINTF(MC146818, "RTC Timer Interrupt\n");
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schedule(curTick + ticksPerSecond/RTC_RATE);
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//Actually interrupt the processor here
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tsunami->cchip->postRTC();
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}
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const char *
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TsunamiIO::RTCEvent::description()
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{
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return "tsunami RTC 1024Hz interrupt";
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}
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// Timer Event for PIT Timers
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TsunamiIO::ClockEvent::ClockEvent()
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: Event(&mainEventQueue)
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{
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DPRINTF(Tsunami, "Clock Event Initilizing\n");
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mode = 0;
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}
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void
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TsunamiIO::ClockEvent::process()
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{
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DPRINTF(Tsunami, "Timer Interrupt\n");
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if (mode == 0)
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status = 0x20; // set bit that linux is looking for
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else
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schedule(curTick + interval);
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}
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void
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TsunamiIO::ClockEvent::Program(int count)
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{
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DPRINTF(Tsunami, "Timer set to curTick + %d\n", count);
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// should be count * (cpufreq/pitfreq)
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interval = count * ticksPerSecond/1193180UL;
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schedule(curTick + interval);
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status = 0;
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}
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const char *
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TsunamiIO::ClockEvent::description()
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{
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return "tsunami 8254 Interval timer";
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}
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void
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TsunamiIO::ClockEvent::ChangeMode(uint8_t md)
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{
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mode = md;
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}
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uint8_t
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TsunamiIO::ClockEvent::Status()
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{
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return status;
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}
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TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
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Addr a, MemoryController *mmu)
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: FunctionalMemory(name), addr(a), tsunami(t), rtc(t)
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{
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mmu->add_child(this, Range<Addr>(addr, addr + size));
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// set the back pointer from tsunami to myself
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tsunami->io = this;
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timerData = 0;
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set_time(init_time == 0 ? time(NULL) : init_time);
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uip = 1;
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picr = 0;
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picInterrupting = false;
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}
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void
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TsunamiIO::set_time(time_t t)
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{
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gmtime_r(&t, &tm);
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DPRINTFN("Real-time clock set to %s", asctime(&tm));
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}
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Fault
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TsunamiIO::read(MemReqPtr &req, uint8_t *data)
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{
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DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n",
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req->vaddr, req->size, req->vaddr & 0xfff);
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Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
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switch(req->size) {
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case sizeof(uint8_t):
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switch(daddr) {
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case TSDEV_PIC1_ISR:
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// !!! If this is modified 64bit case needs to be too
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// Pal code has to do a 64 bit physical read because there is
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// no load physical byte instruction
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*(uint8_t*)data = picr;
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return No_Fault;
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case TSDEV_PIC2_ISR:
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// PIC2 not implemnted... just return 0
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*(uint8_t*)data = 0x00;
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return No_Fault;
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case TSDEV_TMR_CTL:
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*(uint8_t*)data = timer2.Status();
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return No_Fault;
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case TSDEV_RTC_DATA:
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switch(RTCAddress) {
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case RTC_CONTROL_REGISTERA:
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*(uint8_t*)data = uip << 7 | 0x26;
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uip = !uip;
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return No_Fault;
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case RTC_CONTROL_REGISTERB:
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// DM and 24/12 and UIE
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*(uint8_t*)data = 0x46;
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return No_Fault;
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case RTC_CONTROL_REGISTERC:
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// If we want to support RTC user access in linux
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// This won't work, but for now it's fine
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*(uint8_t*)data = 0x00;
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return No_Fault;
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case RTC_CONTROL_REGISTERD:
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panic("RTC Control Register D not implemented");
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case RTC_SECOND:
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*(uint8_t *)data = tm.tm_sec;
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return No_Fault;
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case RTC_MINUTE:
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*(uint8_t *)data = tm.tm_min;
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return No_Fault;
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case RTC_HOUR:
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*(uint8_t *)data = tm.tm_hour;
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return No_Fault;
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case RTC_DAY_OF_WEEK:
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*(uint8_t *)data = tm.tm_wday;
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return No_Fault;
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case RTC_DAY_OF_MONTH:
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*(uint8_t *)data = tm.tm_mday;
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case RTC_MONTH:
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*(uint8_t *)data = tm.tm_mon + 1;
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return No_Fault;
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case RTC_YEAR:
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*(uint8_t *)data = tm.tm_year - UNIX_YEAR_OFFSET;
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return No_Fault;
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default:
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panic("Unknown RTC Address\n");
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}
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default:
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panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
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}
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case sizeof(uint16_t):
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case sizeof(uint32_t):
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panic("I/O Read - invalid size - va %#x size %d\n",
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req->vaddr, req->size);
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_PIC1_ISR:
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// !!! If this is modified 8bit case needs to be too
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// Pal code has to do a 64 bit physical read because there is
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// no load physical byte instruction
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*(uint64_t*)data = (uint64_t)picr;
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return No_Fault;
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default:
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panic("I/O Read - invalid size - va %#x size %d\n",
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req->vaddr, req->size);
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}
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default:
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panic("I/O Read - invalid size - va %#x size %d\n",
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req->vaddr, req->size);
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}
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panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
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return No_Fault;
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}
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Fault
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TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
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{
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uint8_t dt = *(uint8_t*)data;
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uint64_t dt64 = dt;
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DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
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req->vaddr, req->size, req->vaddr & 0xfff, dt64);
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Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
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switch(req->size) {
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case sizeof(uint8_t):
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switch(daddr) {
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case TSDEV_PIC1_MASK:
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mask1 = ~(*(uint8_t*)data);
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if ((picr & mask1) && !picInterrupting) {
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picInterrupting = true;
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tsunami->cchip->postDRIR(55);
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DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
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}
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if ((!(picr & mask1)) && picInterrupting) {
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picInterrupting = false;
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tsunami->cchip->clearDRIR(55);
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DPRINTF(Tsunami, "clearing pic interrupt\n");
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}
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return No_Fault;
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case TSDEV_PIC2_MASK:
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mask2 = *(uint8_t*)data;
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//PIC2 Not implemented to interrupt
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return No_Fault;
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case TSDEV_PIC1_ACK:
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// clear the interrupt on the PIC
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picr &= ~(1 << (*(uint8_t*)data & 0xF));
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if (!(picr & mask1))
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tsunami->cchip->clearDRIR(55);
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return No_Fault;
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case TSDEV_PIC2_ACK:
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return No_Fault;
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case TSDEV_DMA1_RESET:
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return No_Fault;
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case TSDEV_DMA2_RESET:
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return No_Fault;
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case TSDEV_DMA1_MODE:
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mode1 = *(uint8_t*)data;
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return No_Fault;
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case TSDEV_DMA2_MODE:
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mode2 = *(uint8_t*)data;
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return No_Fault;
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case TSDEV_DMA1_MASK:
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case TSDEV_DMA2_MASK:
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return No_Fault;
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case TSDEV_TMR_CTL:
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return No_Fault;
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case TSDEV_TMR2_CTL:
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if ((*(uint8_t*)data & 0x30) != 0x30)
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panic("Only L/M write supported\n");
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switch(*(uint8_t*)data >> 6) {
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case 0:
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timer0.ChangeMode((*(uint8_t*)data & 0xF) >> 1);
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break;
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case 2:
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timer2.ChangeMode((*(uint8_t*)data & 0xF) >> 1);
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break;
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default:
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panic("Read Back Command not implemented\n");
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}
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return No_Fault;
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case TSDEV_TMR2_DATA:
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/* two writes before we actually start the Timer
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so I set a flag in the timerData */
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if(timerData & 0x1000) {
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timerData &= 0x1000;
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timerData += *(uint8_t*)data << 8;
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timer2.Program(timerData);
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} else {
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timerData = *(uint8_t*)data;
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timerData |= 0x1000;
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}
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return No_Fault;
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case TSDEV_TMR0_DATA:
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/* two writes before we actually start the Timer
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so I set a flag in the timerData */
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if(timerData & 0x1000) {
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timerData &= 0x1000;
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timerData += *(uint8_t*)data << 8;
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timer0.Program(timerData);
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} else {
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timerData = *(uint8_t*)data;
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timerData |= 0x1000;
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}
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return No_Fault;
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case TSDEV_RTC_ADDR:
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RTCAddress = *(uint8_t*)data;
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return No_Fault;
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case TSDEV_RTC_DATA:
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panic("RTC Write not implmented (rtc.o won't work)\n");
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default:
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panic("I/O Write - va%#x size %d\n", req->vaddr, req->size);
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}
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case sizeof(uint16_t):
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case sizeof(uint32_t):
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case sizeof(uint64_t):
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default:
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panic("I/O Write - invalid size - va %#x size %d\n",
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req->vaddr, req->size);
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}
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return No_Fault;
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}
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void
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TsunamiIO::postPIC(uint8_t bitvector)
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{
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//PIC2 Is not implemented, because nothing of interest there
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picr |= bitvector;
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if (picr & mask1) {
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tsunami->cchip->postDRIR(55);
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DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
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}
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}
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void
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TsunamiIO::clearPIC(uint8_t bitvector)
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{
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//PIC2 Is not implemented, because nothing of interest there
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picr &= ~bitvector;
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if (!(picr & mask1)) {
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tsunami->cchip->clearDRIR(55);
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DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
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}
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}
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void
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TsunamiIO::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(timerData);
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SERIALIZE_SCALAR(uip);
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SERIALIZE_SCALAR(picr);
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SERIALIZE_SCALAR(picInterrupting);
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Tick time0when = timer0.when();
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Tick time2when = timer2.when();
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Tick rtcwhen = rtc.when();
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SERIALIZE_SCALAR(time0when);
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SERIALIZE_SCALAR(time2when);
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SERIALIZE_SCALAR(rtcwhen);
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}
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void
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TsunamiIO::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(timerData);
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UNSERIALIZE_SCALAR(uip);
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UNSERIALIZE_SCALAR(picr);
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UNSERIALIZE_SCALAR(picInterrupting);
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Tick time0when;
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Tick time2when;
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Tick rtcwhen;
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UNSERIALIZE_SCALAR(time0when);
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UNSERIALIZE_SCALAR(time2when);
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UNSERIALIZE_SCALAR(rtcwhen);
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timer0.reschedule(time0when);
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timer2.reschedule(time2when);
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rtc.reschedule(rtcwhen);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
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SimObjectParam<Tsunami *> tsunami;
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Param<time_t> time;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
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BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
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INIT_PARAM(tsunami, "Tsunami"),
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INIT_PARAM_DFLT(time, "System time to use "
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"(0 for actual time, default is 1/1/06", ULL(1136073600)),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address")
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END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
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CREATE_SIM_OBJECT(TsunamiIO)
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{
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return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu);
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}
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REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
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