gem5/tests/configs/o3-timing-checker.py
Andreas Hansson 9cbe1cb653 config: Unify caches used in regressions and adjust L2 MSHRs
This patch unified the L1 and L2 caches used throughout the
regressions instead of declaring different, but very similar,
configurations in the different scripts.

The patch also changes the default L2 configuration to match what it
used to be for the fs and se scripts (until the last patch that
updated the regressions to also make use of the cache config). The
MSHRs and targets per MSHR are now set to a more realistic default of
20 and 12, respectively.

As a result of both the aforementioned changes, many of the regression
stats are changed. A follow-on patch will bump the stats.
2012-10-30 07:44:08 -04:00

61 lines
2.8 KiB
Python

# Copyright (c) 2011 ARM Limited
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# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
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# this software without specific prior written permission.
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# Authors: Geoffrey Blake
import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
from Caches import *
cpu = DerivO3CPU(cpu_id=0)
cpu.createInterruptController()
cpu.addCheckerCpu()
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
L1Cache(size = '256kB'),
L2Cache(size = '2MB'))
# @todo Note that the L2 latency here is unmodified and 2 cycles,
# should set hit latency and response latency to 20 cycles as for
# other scripts
cpu.clock = '2GHz'
system = System(cpu = cpu,
physmem = SimpleDRAM(),
membus = CoherentBus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
cpu.connectAllPorts(system.membus)
root = Root(full_system = False, system = system)