2308f812ef
This patch makes the buses multi layered, and effectively creates a crossbar structure with distributed contention ports at the destination ports. Before this patch, a bus could have a single request, response and snoop response in flight at any time, and with these changes there can be as many requests as connected slaves (bus master ports), and as many responses as connected masters (bus slave ports). Together with address interleaving, this patch enables us to create high-throughput memory interconnects, e.g. 50+ GByte/s.
307 lines
10 KiB
C++
307 lines
10 KiB
C++
/*
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* Copyright (c) 2011-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Andreas Hansson
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* William Wang
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*/
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/**
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* @file
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* Definition of a bus object.
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*/
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "debug/Bus.hh"
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#include "debug/BusAddrRanges.hh"
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#include "debug/NoncoherentBus.hh"
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#include "mem/noncoherent_bus.hh"
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NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p)
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: BaseBus(p)
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{
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// create the ports based on the size of the master and slave
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// vector ports, and the presence of the default port, the ports
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// are enumerated starting from zero
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for (int i = 0; i < p->port_master_connection_count; ++i) {
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std::string portName = csprintf("%s.master[%d]", name(), i);
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MasterPort* bp = new NoncoherentBusMasterPort(portName, *this, i);
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masterPorts.push_back(bp);
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reqLayers.push_back(new ReqLayer(*bp, *this,
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csprintf(".reqLayer%d", i)));
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}
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// see if we have a default slave device connected and if so add
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// our corresponding master port
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if (p->port_default_connection_count) {
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defaultPortID = masterPorts.size();
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std::string portName = name() + ".default";
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MasterPort* bp = new NoncoherentBusMasterPort(portName, *this,
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defaultPortID);
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masterPorts.push_back(bp);
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reqLayers.push_back(new ReqLayer(*bp, *this, csprintf(".reqLayer%d",
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defaultPortID)));
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}
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// create the slave ports, once again starting at zero
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for (int i = 0; i < p->port_slave_connection_count; ++i) {
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std::string portName = csprintf("%s.slave[%d]", name(), i);
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SlavePort* bp = new NoncoherentBusSlavePort(portName, *this, i);
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slavePorts.push_back(bp);
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respLayers.push_back(new RespLayer(*bp, *this,
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csprintf(".respLayer%d", i)));
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}
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clearPortCache();
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}
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NoncoherentBus::~NoncoherentBus()
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{
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for (auto l = reqLayers.begin(); l != reqLayers.end(); ++l)
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delete *l;
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for (auto l = respLayers.begin(); l != respLayers.end(); ++l)
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delete *l;
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}
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bool
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NoncoherentBus::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
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{
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// determine the source port based on the id
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SlavePort *src_port = slavePorts[slave_port_id];
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// we should never see express snoops on a non-coherent bus
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assert(!pkt->isExpressSnoop());
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// determine the destination based on the address
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PortID master_port_id = findPort(pkt->getAddr());
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// test if the bus should be considered occupied for the current
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// port
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if (!reqLayers[master_port_id]->tryTiming(src_port)) {
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DPRINTF(NoncoherentBus, "recvTimingReq: src %s %s 0x%x BUSY\n",
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src_port->name(), pkt->cmdString(), pkt->getAddr());
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return false;
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}
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DPRINTF(NoncoherentBus, "recvTimingReq: src %s %s 0x%x\n",
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src_port->name(), pkt->cmdString(), pkt->getAddr());
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// store size and command as they might be modified when
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// forwarding the packet
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unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
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unsigned int pkt_cmd = pkt->cmdToIndex();
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// set the source port for routing of the response
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pkt->setSrc(slave_port_id);
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calcPacketTiming(pkt);
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Tick packetFinishTime = pkt->busLastWordDelay + curTick();
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// since it is a normal request, attempt to send the packet
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bool success = masterPorts[master_port_id]->sendTimingReq(pkt);
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if (!success) {
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// inhibited packets should never be forced to retry
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assert(!pkt->memInhibitAsserted());
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DPRINTF(NoncoherentBus, "recvTimingReq: src %s %s 0x%x RETRY\n",
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src_port->name(), pkt->cmdString(), pkt->getAddr());
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// undo the calculation so we can check for 0 again
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pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
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// occupy until the header is sent
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reqLayers[master_port_id]->failedTiming(src_port,
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clockEdge(headerCycles));
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return false;
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}
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reqLayers[master_port_id]->succeededTiming(packetFinishTime);
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// stats updates
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dataThroughBus += pkt_size;
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pktCount[slave_port_id][master_port_id]++;
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totPktSize[slave_port_id][master_port_id] += pkt_size;
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transDist[pkt_cmd]++;
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return true;
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}
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bool
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NoncoherentBus::recvTimingResp(PacketPtr pkt, PortID master_port_id)
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{
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// determine the source port based on the id
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MasterPort *src_port = masterPorts[master_port_id];
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// determine the destination based on what is stored in the packet
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PortID slave_port_id = pkt->getDest();
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// test if the bus should be considered occupied for the current
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// port
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if (!respLayers[slave_port_id]->tryTiming(src_port)) {
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DPRINTF(NoncoherentBus, "recvTimingResp: src %s %s 0x%x BUSY\n",
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src_port->name(), pkt->cmdString(), pkt->getAddr());
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return false;
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}
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DPRINTF(NoncoherentBus, "recvTimingResp: src %s %s 0x%x\n",
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src_port->name(), pkt->cmdString(), pkt->getAddr());
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// store size and command as they might be modified when
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// forwarding the packet
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unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
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unsigned int pkt_cmd = pkt->cmdToIndex();
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calcPacketTiming(pkt);
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Tick packetFinishTime = pkt->busLastWordDelay + curTick();
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// send the packet through the destination slave port
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bool success M5_VAR_USED = slavePorts[slave_port_id]->sendTimingResp(pkt);
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// currently it is illegal to block responses... can lead to
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// deadlock
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assert(success);
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respLayers[slave_port_id]->succeededTiming(packetFinishTime);
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// stats updates
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dataThroughBus += pkt_size;
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pktCount[slave_port_id][master_port_id]++;
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totPktSize[slave_port_id][master_port_id] += pkt_size;
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transDist[pkt_cmd]++;
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return true;
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}
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void
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NoncoherentBus::recvRetry(PortID master_port_id)
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{
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// responses never block on forwarding them, so the retry will
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// always be coming from a port to which we tried to forward a
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// request
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reqLayers[master_port_id]->recvRetry();
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}
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Tick
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NoncoherentBus::recvAtomic(PacketPtr pkt, PortID slave_port_id)
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{
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DPRINTF(NoncoherentBus, "recvAtomic: packet src %s addr 0x%x cmd %s\n",
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slavePorts[slave_port_id]->name(), pkt->getAddr(),
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pkt->cmdString());
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// add the request data
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dataThroughBus += pkt->hasData() ? pkt->getSize() : 0;
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// determine the destination port
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PortID dest_id = findPort(pkt->getAddr());
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// forward the request to the appropriate destination
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Tick response_latency = masterPorts[dest_id]->sendAtomic(pkt);
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// add the response data
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if (pkt->isResponse())
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dataThroughBus += pkt->hasData() ? pkt->getSize() : 0;
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// @todo: Not setting first-word time
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pkt->busLastWordDelay = response_latency;
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return response_latency;
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}
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void
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NoncoherentBus::recvFunctional(PacketPtr pkt, PortID slave_port_id)
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{
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if (!pkt->isPrint()) {
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// don't do DPRINTFs on PrintReq as it clutters up the output
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DPRINTF(NoncoherentBus,
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"recvFunctional: packet src %s addr 0x%x cmd %s\n",
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slavePorts[slave_port_id]->name(), pkt->getAddr(),
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pkt->cmdString());
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}
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// determine the destination port
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PortID dest_id = findPort(pkt->getAddr());
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// forward the request to the appropriate destination
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masterPorts[dest_id]->sendFunctional(pkt);
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}
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unsigned int
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NoncoherentBus::drain(DrainManager *dm)
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{
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// sum up the individual layers
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unsigned int total = 0;
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for (auto l = reqLayers.begin(); l != reqLayers.end(); ++l)
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total += (*l)->drain(dm);
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for (auto l = respLayers.begin(); l != respLayers.end(); ++l)
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total += (*l)->drain(dm);
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return total;
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}
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NoncoherentBus*
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NoncoherentBusParams::create()
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{
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return new NoncoherentBus(this);
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}
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void
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NoncoherentBus::regStats()
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{
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// register the stats of the base class and our two bus layers
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BaseBus::regStats();
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for (auto l = reqLayers.begin(); l != reqLayers.end(); ++l)
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(*l)->regStats();
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for (auto l = respLayers.begin(); l != respLayers.end(); ++l)
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(*l)->regStats();
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dataThroughBus
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.name(name() + ".data_through_bus")
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.desc("Total data (bytes)")
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;
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throughput
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.name(name() + ".throughput")
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.desc("Throughput (bytes/s)")
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.precision(0)
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;
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throughput = dataThroughBus / simSeconds;
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}
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