0cacf7e817
This patch addresses the comments and feedback on the preceding patch that reworks the clocks and now more clearly shows where cycles (relative cycle counts) are used to express time. Instead of bumping the existing patch I chose to make this a separate patch, merely to try and focus the discussion around a smaller set of changes. The two patches will be pushed together though. This changes done as part of this patch are mostly following directly from the introduction of the wrapper class, and change enough code to make things compile and run again. There are definitely more places where int/uint/Tick is still used to represent cycles, and it will take some time to chase them all down. Similarly, a lot of parameters should be changed from Param.Tick and Param.Unsigned to Param.Cycles. In addition, the use of curTick is questionable as there should not be an absolute cycle. Potential solutions can be built on top of this patch. There is a similar situation in the o3 CPU where lastRunningCycle is currently counting in Cycles, and is still an absolute time. More discussion to be had in other words. An additional change that would be appropriate in the future is to perform a similar wrapping of Tick and probably also introduce a Ticks class along with suitable operators for all these classes.
376 lines
13 KiB
C++
376 lines
13 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/sparc/isa.hh"
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#include "arch/sparc/kernel_stats.hh"
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#include "arch/sparc/registers.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Quiesce.hh"
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#include "debug/Timer.hh"
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#include "sim/system.hh"
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#include "sim/full_system.hh"
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using namespace SparcISA;
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using namespace std;
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void
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ISA::checkSoftInt(ThreadContext *tc)
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{
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BaseCPU *cpu = tc->getCpuPtr();
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// If PIL < 14, copy over the tm and sm bits
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if (pil < 14 && softint & 0x10000)
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cpu->postInterrupt(IT_SOFT_INT, 16);
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else
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cpu->clearInterrupt(IT_SOFT_INT, 16);
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if (pil < 14 && softint & 0x1)
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cpu->postInterrupt(IT_SOFT_INT, 0);
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else
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cpu->clearInterrupt(IT_SOFT_INT, 0);
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// Copy over any of the other bits that are set
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for (int bit = 15; bit > 0; --bit) {
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if (1 << bit & softint && bit > pil)
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cpu->postInterrupt(IT_SOFT_INT, bit);
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else
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cpu->clearInterrupt(IT_SOFT_INT, bit);
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}
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}
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// These functions map register indices to names
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static inline string
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getMiscRegName(RegIndex index)
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{
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static string miscRegName[NumMiscRegs] =
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{/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
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"gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
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"stick", "stick_cmpr",
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"tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
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"pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
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"wstate",*/ "gl",
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"hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
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"hstick_cmpr",
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"fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
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"scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
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"scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
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"devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
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"nresErrorHead", "nresErrorTail", "TlbData" };
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return miscRegName[index];
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}
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void
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ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
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{
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BaseCPU *cpu = tc->getCpuPtr();
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int64_t time;
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switch (miscReg) {
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/* Full system only ASRs */
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case MISCREG_SOFTINT:
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setMiscRegNoEffect(miscReg, val);;
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checkSoftInt(tc);
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break;
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case MISCREG_SOFTINT_CLR:
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return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc);
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case MISCREG_SOFTINT_SET:
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return setMiscReg(MISCREG_SOFTINT, val | softint, tc);
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case MISCREG_TICK_CMPR:
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if (tickCompare == NULL)
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tickCompare = new TickCompareEvent(this, tc);
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setMiscRegNoEffect(miscReg, val);
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if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
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cpu->deschedule(tickCompare);
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time = (tick_cmpr & mask(63)) - (tick & mask(63));
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if (!(tick_cmpr & ~mask(63)) && time > 0) {
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if (tickCompare->scheduled())
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cpu->deschedule(tickCompare);
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cpu->schedule(tickCompare, cpu->clockEdge(Cycles(time)));
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}
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panic("writing to TICK compare register %#X\n", val);
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break;
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case MISCREG_STICK_CMPR:
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if (sTickCompare == NULL)
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sTickCompare = new STickCompareEvent(this, tc);
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setMiscRegNoEffect(miscReg, val);
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if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
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cpu->deschedule(sTickCompare);
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time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
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cpu->instCount();
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if (!(stick_cmpr & ~mask(63)) && time > 0) {
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if (sTickCompare->scheduled())
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cpu->deschedule(sTickCompare);
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cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(time)));
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}
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DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
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break;
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case MISCREG_PSTATE:
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setMiscRegNoEffect(miscReg, val);
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case MISCREG_PIL:
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setMiscRegNoEffect(miscReg, val);
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checkSoftInt(tc);
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break;
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case MISCREG_HVER:
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panic("Shouldn't be writing HVER\n");
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case MISCREG_HINTP:
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setMiscRegNoEffect(miscReg, val);
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if (hintp)
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cpu->postInterrupt(IT_HINTP, 0);
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else
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cpu->clearInterrupt(IT_HINTP, 0);
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break;
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case MISCREG_HTBA:
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// clear lower 7 bits on writes.
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setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF));
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break;
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case MISCREG_QUEUE_CPU_MONDO_HEAD:
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case MISCREG_QUEUE_CPU_MONDO_TAIL:
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setMiscRegNoEffect(miscReg, val);
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if (cpu_mondo_head != cpu_mondo_tail)
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cpu->postInterrupt(IT_CPU_MONDO, 0);
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else
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cpu->clearInterrupt(IT_CPU_MONDO, 0);
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break;
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case MISCREG_QUEUE_DEV_MONDO_HEAD:
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case MISCREG_QUEUE_DEV_MONDO_TAIL:
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setMiscRegNoEffect(miscReg, val);
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if (dev_mondo_head != dev_mondo_tail)
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cpu->postInterrupt(IT_DEV_MONDO, 0);
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else
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cpu->clearInterrupt(IT_DEV_MONDO, 0);
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break;
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case MISCREG_QUEUE_RES_ERROR_HEAD:
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case MISCREG_QUEUE_RES_ERROR_TAIL:
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setMiscRegNoEffect(miscReg, val);
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if (res_error_head != res_error_tail)
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cpu->postInterrupt(IT_RES_ERROR, 0);
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else
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cpu->clearInterrupt(IT_RES_ERROR, 0);
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break;
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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setMiscRegNoEffect(miscReg, val);
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// This one doesn't have an interrupt to report to the guest OS
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break;
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case MISCREG_HSTICK_CMPR:
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if (hSTickCompare == NULL)
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hSTickCompare = new HSTickCompareEvent(this, tc);
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setMiscRegNoEffect(miscReg, val);
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if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
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cpu->deschedule(hSTickCompare);
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time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
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cpu->instCount();
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if (!(hstick_cmpr & ~mask(63)) && time > 0) {
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if (hSTickCompare->scheduled())
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cpu->deschedule(hSTickCompare);
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cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(time)));
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}
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DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
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break;
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case MISCREG_HPSTATE:
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{
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HPSTATE newVal = val;
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newVal.id = 1;
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// T1000 spec says impl. dependent val must always be 1
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setMiscRegNoEffect(miscReg, newVal);
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newVal = hpstate;
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if (newVal.tlz && tl == 0 && !newVal.hpriv)
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cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
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else
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cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
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break;
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}
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case MISCREG_HTSTATE:
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setMiscRegNoEffect(miscReg, val);
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break;
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case MISCREG_STRAND_STS_REG:
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if (bits(val,2,2))
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panic("No support for setting spec_en bit\n");
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setMiscRegNoEffect(miscReg, bits(val,0,0));
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if (!bits(val,0,0)) {
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DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
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// Time to go to sleep
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tc->suspend();
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if (FullSystem && tc->getKernelStats())
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tc->getKernelStats()->quiesce();
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}
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break;
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default:
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panic("Invalid write to FS misc register %s\n",
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getMiscRegName(miscReg));
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}
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}
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MiscReg
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ISA::readFSReg(int miscReg, ThreadContext * tc)
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{
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uint64_t temp;
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switch (miscReg) {
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/* Privileged registers. */
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case MISCREG_QUEUE_CPU_MONDO_HEAD:
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case MISCREG_QUEUE_CPU_MONDO_TAIL:
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case MISCREG_QUEUE_DEV_MONDO_HEAD:
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case MISCREG_QUEUE_DEV_MONDO_TAIL:
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case MISCREG_QUEUE_RES_ERROR_HEAD:
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case MISCREG_QUEUE_RES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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case MISCREG_SOFTINT:
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case MISCREG_TICK_CMPR:
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case MISCREG_STICK_CMPR:
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case MISCREG_PIL:
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case MISCREG_HPSTATE:
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case MISCREG_HINTP:
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case MISCREG_HTSTATE:
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case MISCREG_HSTICK_CMPR:
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return readMiscRegNoEffect(miscReg) ;
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case MISCREG_HTBA:
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return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF);
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case MISCREG_HVER:
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// XXX set to match Legion
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return ULL(0x3e) << 48 |
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ULL(0x23) << 32 |
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ULL(0x20) << 24 |
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// MaxGL << 16 | XXX For some reason legion doesn't set GL
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MaxTL << 8 |
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(NWindows -1) << 0;
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case MISCREG_STRAND_STS_REG:
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System *sys;
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int x;
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sys = tc->getSystemPtr();
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temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative);
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// Check that the CPU array is fully populated
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// (by calling getNumCPus())
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assert(sys->numContexts() > tc->contextId());
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temp |= tc->contextId() << STS::shft_id;
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for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) {
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switch (sys->threadContexts[x]->status()) {
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case ThreadContext::Active:
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temp |= STS::st_run << (STS::shft_fsm0 -
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((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
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break;
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case ThreadContext::Suspended:
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// should this be idle?
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temp |= STS::st_idle << (STS::shft_fsm0 -
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((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
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break;
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case ThreadContext::Halted:
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temp |= STS::st_halt << (STS::shft_fsm0 -
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((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
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break;
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default:
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panic("What state are we in?!\n");
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} // switch
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} // for
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return temp;
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default:
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panic("Invalid read to FS misc register\n");
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}
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}
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void
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ISA::processTickCompare(ThreadContext *tc)
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{
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panic("tick compare not implemented\n");
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}
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void
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ISA::processSTickCompare(ThreadContext *tc)
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{
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BaseCPU *cpu = tc->getCpuPtr();
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// since our microcode instructions take two cycles we need to check if
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// we're actually at the correct cycle or we need to wait a little while
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// more
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int delay;
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delay = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
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cpu->instCount();
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assert(delay >= 0 && "stick compare missed interrupt cycle");
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if (delay == 0 || tc->status() == ThreadContext::Suspended) {
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DPRINTF(Timer, "STick compare cycle reached at %#x\n",
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(stick_cmpr & mask(63)));
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if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
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setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
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}
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} else {
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cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(delay)));
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}
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}
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void
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ISA::processHSTickCompare(ThreadContext *tc)
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{
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BaseCPU *cpu = tc->getCpuPtr();
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// since our microcode instructions take two cycles we need to check if
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// we're actually at the correct cycle or we need to wait a little while
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// more
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int delay;
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if ( tc->status() == ThreadContext::Halted)
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return;
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delay = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
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cpu->instCount();
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assert(delay >= 0 && "hstick compare missed interrupt cycle");
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if (delay == 0 || tc->status() == ThreadContext::Suspended) {
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DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
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(stick_cmpr & mask(63)));
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if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
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setMiscReg(MISCREG_HINTP, 1, tc);
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}
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// Need to do something to cause interrupt to happen here !!! @todo
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} else {
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cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(delay)));
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}
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}
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