9bc132e473
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
85 lines
8.9 KiB
Plaintext
85 lines
8.9 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000125 # Number of seconds simulated
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sim_ticks 125334 # Number of ticks simulated
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final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000 # Frequency of simulated ticks
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host_inst_rate 34119 # Simulator instruction rate (inst/s)
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host_op_rate 34115 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 735344 # Simulator tick rate (ticks/s)
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host_mem_usage 282376 # Number of bytes of host memory used
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host_seconds 0.17 # Real time elapsed on the host
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sim_insts 5814 # Number of instructions simulated
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sim_ops 5814 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 4374 # Number of bytes read from this memory
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system.physmem.bytes_read::total 27634 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 23260 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 23260 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu.data 3658 # Number of bytes written to this memory
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system.physmem.bytes_written::total 3658 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 5815 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1163 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 6978 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu.data 925 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 925 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 185584119 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 34898751 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 220482870 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 185584119 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 185584119 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 29186015 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 29186015 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 185584119 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 64084766 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 249668885 # Total bandwidth to/from this memory (bytes/s)
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system.ruby.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads
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system.ruby.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes
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system.ruby.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads
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system.ruby.l1_cntrl0.cacheMemory.num_tag_array_writes 0 # number of tag array writes
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system.ruby.l1_cntrl0.cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
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system.ruby.l1_cntrl0.cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 8 # Number of system calls
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system.cpu.numCycles 125334 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 5814 # Number of instructions committed
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system.cpu.committedOps 5814 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
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system.cpu.num_func_calls 194 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls
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system.cpu.num_int_insts 5113 # number of integer instructions
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system.cpu.num_fp_insts 2 # number of float instructions
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system.cpu.num_int_register_reads 7284 # number of times the integer registers were read
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system.cpu.num_int_register_writes 3397 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
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system.cpu.num_mem_refs 2089 # number of memory refs
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system.cpu.num_load_insts 1163 # Number of load instructions
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system.cpu.num_store_insts 926 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 125334 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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---------- End Simulation Statistics ----------
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