c86f849d5a
This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch.
59 lines
2.5 KiB
Python
59 lines
2.5 KiB
Python
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
|
# All rights reserved.
|
|
#
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions are
|
|
# met: redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer;
|
|
# redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
# documentation and/or other materials provided with the distribution;
|
|
# neither the name of the copyright holders nor the names of its
|
|
# contributors may be used to endorse or promote products derived from
|
|
# this software without specific prior written permission.
|
|
#
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
#
|
|
# Authors: Steve Reinhardt
|
|
# Brad Beckmann
|
|
|
|
from m5.params import *
|
|
from m5.proxy import *
|
|
from MemObject import MemObject
|
|
|
|
class RubyPort(MemObject):
|
|
type = 'RubyPort'
|
|
abstract = True
|
|
port = VectorPort("M5 port")
|
|
version = Param.Int(0, "")
|
|
pio_port = Port("Ruby_pio_port")
|
|
physmem = Param.PhysicalMemory("")
|
|
physMemPort = Port("port to physical memory")
|
|
using_ruby_tester = Param.Bool(False, "")
|
|
using_network_tester = Param.Bool(False, "")
|
|
access_phys_mem = Param.Bool(True,
|
|
"should the rubyport atomically update phys_mem")
|
|
ruby_system = Param.RubySystem("")
|
|
|
|
class RubySequencer(RubyPort):
|
|
type = 'RubySequencer'
|
|
cxx_class = 'Sequencer'
|
|
icache = Param.RubyCache("")
|
|
dcache = Param.RubyCache("")
|
|
max_outstanding_requests = Param.Int(16,
|
|
"max requests (incl. prefetches) outstanding")
|
|
deadlock_threshold = Param.Int(500000,
|
|
"max outstanding cycles for a request before deadlock/livelock declared")
|
|
|
|
class DMASequencer(RubyPort):
|
|
type = 'DMASequencer'
|