2889 lines
330 KiB
Text
2889 lines
330 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000108 # Number of seconds simulated
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sim_ticks 107700000 # Number of ticks simulated
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final_tick 107700000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 68250 # Simulator instruction rate (inst/s)
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host_op_rate 68250 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 7391011 # Simulator tick rate (ticks/s)
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host_mem_usage 243816 # Number of bytes of host memory used
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host_seconds 14.57 # Real time elapsed on the host
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sim_insts 994522 # Number of instructions simulated
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sim_ops 994522 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
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system.physmem.bytes_read::total 42560 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 665 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 213927577 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 100427112 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 48727948 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 11884865 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 3565460 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 7725162 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.inst 1188487 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.data 7725162 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 395171773 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 213927577 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 48727948 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 3565460 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu3.inst 1188487 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 267409471 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 213927577 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 100427112 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 48727948 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 11884865 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 3565460 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 7725162 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.inst 1188487 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.data 7725162 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 395171773 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 666 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 42624 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 42624 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 114 # Per bank write bursts
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system.physmem.perBankRdBursts::1 42 # Per bank write bursts
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system.physmem.perBankRdBursts::2 30 # Per bank write bursts
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system.physmem.perBankRdBursts::3 60 # Per bank write bursts
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system.physmem.perBankRdBursts::4 66 # Per bank write bursts
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system.physmem.perBankRdBursts::5 27 # Per bank write bursts
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system.physmem.perBankRdBursts::6 18 # Per bank write bursts
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system.physmem.perBankRdBursts::7 24 # Per bank write bursts
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system.physmem.perBankRdBursts::8 7 # Per bank write bursts
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system.physmem.perBankRdBursts::9 28 # Per bank write bursts
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system.physmem.perBankRdBursts::10 23 # Per bank write bursts
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system.physmem.perBankRdBursts::11 13 # Per bank write bursts
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system.physmem.perBankRdBursts::12 61 # Per bank write bursts
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system.physmem.perBankRdBursts::13 38 # Per bank write bursts
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system.physmem.perBankRdBursts::14 18 # Per bank write bursts
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system.physmem.perBankRdBursts::15 97 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 107672000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 666 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 396 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 199 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 145 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 274.537931 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 187.244268 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 251.506931 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 44 30.34% 30.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 37 25.52% 55.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 28 19.31% 75.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 11 7.59% 82.76% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 7 4.83% 87.59% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 8 5.52% 93.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation
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system.physmem.totQLat 6586250 # Total ticks spent queuing
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system.physmem.totMemAccLat 19073750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 9889.26 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 28639.26 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 395.77 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 395.77 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 3.09 # Data bus utilization in percentage
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system.physmem.busUtilRead 3.09 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 510 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 161669.67 # Average gap between requests
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system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 38199690 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 27380250 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 76058610 # Total energy per rank (pJ)
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system.physmem_0.averagePower 749.484363 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 47670750 # Time in different power states
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system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 52812250 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 32151420 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 32685750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 74025645 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 729.451450 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 57549250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 43929750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu0.branchPred.lookups 81595 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 78953 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 78929 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 76214 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 96.560200 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.workload.num_syscalls 89 # Number of system calls
|
|
system.cpu0.numCycles 215401 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 19727 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 482343 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 81595 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 76859 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 165670 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingTrapStallCycles 1993 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.CacheLines 6732 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 621 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 188739 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 2.555609 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 2.213598 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 30459 16.14% 16.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 78270 41.47% 57.61% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 797 0.42% 58.03% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 1203 0.64% 58.67% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 613 0.32% 58.99% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 73671 39.03% 98.03% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 2652 1.41% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 188739 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.378805 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 2.239279 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 15463 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 18382 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 152999 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 645 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing
|
|
system.cpu0.decode.DecodedInsts 471851 # Number of instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 16060 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 2005 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 15072 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 152998 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 1354 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 468673 # Number of instructions processed by rename
|
|
system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full
|
|
system.cpu0.rename.SQFullEvents 851 # Number of times rename has blocked due to SQ full
|
|
system.cpu0.rename.RenamedOperands 320440 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 934717 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 705961 # Number of integer rename lookups
|
|
system.cpu0.rename.CommittedMaps 307367 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 13073 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 4337 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 149926 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 75817 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 73307 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 72919 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 392051 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 388622 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 12300 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 11714 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 188739 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 2.059045 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.124370 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 33524 17.76% 17.76% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 4207 2.23% 19.99% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 74141 39.28% 59.27% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 73776 39.09% 98.36% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 1579 0.84% 99.20% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 884 0.47% 99.67% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 404 0.21% 99.88% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 188739 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 61 21.18% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.18% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 124 43.06% 64.24% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 103 35.76% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 164274 42.27% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 149282 38.41% 80.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 75066 19.32% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 388622 # Type of FU issued
|
|
system.cpu0.iq.rate 1.804179 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 288 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.000741 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 966302 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 405302 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 386770 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 388910 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 72419 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 1969 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 466549 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 149926 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 75817 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 387610 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 148943 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 73609 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 223859 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 76931 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 74916 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 1.799481 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 387178 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 386770 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 229443 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 232488 # num instructions consuming a value
|
|
system.cpu0.iew.wb_rate 1.795581 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.986903 # average fanout of values written-back
|
|
system.cpu0.commit.commitSquashedInsts 13089 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 186278 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 2.434007 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 2.148610 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 33753 18.12% 18.12% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 76007 40.80% 58.92% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.96% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 664 0.36% 60.32% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 518 0.28% 60.60% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 72154 38.73% 99.33% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 496 0.27% 99.60% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 186278 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 453402 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 453402 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 221416 # Number of memory references committed
|
|
system.cpu0.commit.loads 147273 # Number of loads committed
|
|
system.cpu0.commit.membars 84 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 76030 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 305698 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 223 # Number of function calls committed.
|
|
system.cpu0.commit.op_class_0::No_OpClass 72762 16.05% 16.05% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntAlu 159140 35.10% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemRead 147357 32.50% 83.65% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemWrite 74143 16.35% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::total 453402 # Class of committed instruction
|
|
system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached
|
|
system.cpu0.rob.rob_reads 651125 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 935459 # The number of ROB writes
|
|
system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 26662 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.committedInsts 380556 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 380556 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.cpi 0.566017 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 0.566017 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 1.766733 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 1.766733 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 693490 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 312678 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
|
|
system.cpu0.misc_regfile_reads 225727 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
|
|
system.cpu0.dcache.tags.replacements 2 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 141.118700 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 149407 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 873.725146 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.118700 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275622 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.275622 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 602739 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 602739 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 75912 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 75912 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 73546 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 73546 # number of WriteReq hits
|
|
system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
|
|
system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 149458 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 149458 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 149458 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 149458 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 553 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 553 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses
|
|
system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
|
|
system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1108 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1108 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1108 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1108 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16789000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 16789000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34744480 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 34744480 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles
|
|
system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 51533480 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 51533480 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 51533480 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 51533480 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 76465 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 76465 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 74101 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 74101 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
|
|
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 150566 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 150566 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 150566 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 150566 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007232 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.007232 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007490 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.007490 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007359 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.007359 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007359 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.007359 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30359.855335 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 30359.855335 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62602.666667 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 62602.666667 # average WriteReq miss latency
|
|
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency
|
|
system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46510.361011 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 46510.361011 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46510.361011 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 46510.361011 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 1 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 370 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 370 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 378 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 378 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 748 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 748 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 748 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 748 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6853000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6853000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8423500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8423500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15276500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 15276500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15276500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 15276500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002393 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002393 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002389 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002391 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002391 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002391 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002391 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37448.087432 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37448.087432 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47590.395480 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47590.395480 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42434.722222 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42434.722222 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42434.722222 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42434.722222 # average overall mshr miss latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 315 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 241.159002 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.159002 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471014 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.471014 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 7339 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 7339 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 5949 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 783 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 783 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 783 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 783 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 783 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 783 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40394500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 40394500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 40394500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 40394500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 40394500 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 40394500 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 6732 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 6732 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 6732 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 6732 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 6732 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 6732 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116310 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.116310 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116310 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.116310 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116310 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.116310 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51589.399745 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 51589.399745 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51589.399745 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 51589.399745 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51589.399745 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 51589.399745 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.writebacks::writebacks 315 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 315 # number of writebacks
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 175 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 175 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 175 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 175 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 608 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31312500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 31312500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31312500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 31312500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31312500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 31312500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090315 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.090315 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.090315 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51500.822368 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 51500.822368 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 51500.822368 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.branchPred.lookups 52270 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 48857 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 1261 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 45038 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 43957 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 97.599805 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 912 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
|
|
system.cpu1.numCycles 162626 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 30636 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 289541 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 52270 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 44869 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 123502 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 21117 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 458 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 156585 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 1.849098 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.199028 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 55186 35.24% 35.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 51235 32.72% 67.96% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 6397 4.09% 72.05% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 3507 2.24% 74.29% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 942 0.60% 74.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 33361 21.31% 96.20% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 1213 0.77% 96.97% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 812 0.52% 97.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 3932 2.51% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 156585 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.321412 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 1.780410 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 17913 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 54188 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 79912 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 3224 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 1338 # Number of cycles decode is squashing
|
|
system.cpu1.decode.DecodedInsts 274398 # Number of instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 1338 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 18610 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 24678 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 13550 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 81416 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 16983 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 271226 # Number of instructions processed by rename
|
|
system.cpu1.rename.IQFullEvents 15241 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full
|
|
system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers
|
|
system.cpu1.rename.RenamedOperands 191192 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 520363 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 405271 # Number of integer rename lookups
|
|
system.cpu1.rename.CommittedMaps 177667 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 13525 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 21370 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 76128 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 36144 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 36135 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 31079 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 225686 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 6135 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 227404 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 12625 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 10115 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 156585 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 1.452272 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.380275 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 58755 37.52% 37.52% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 20747 13.25% 50.77% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 35642 22.76% 73.53% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 35172 22.46% 96.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 3374 2.15% 98.15% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 1612 1.03% 99.18% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 878 0.56% 99.74% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 207 0.13% 99.87% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 198 0.13% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 156585 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 79 24.01% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.01% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 41 12.46% 36.47% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 209 63.53% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 111654 49.10% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 80158 35.25% 84.35% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 35592 15.65% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 227404 # Type of FU issued
|
|
system.cpu1.iq.rate 1.398325 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 329 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.001447 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 611730 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 244482 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 225916 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 227733 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 30932 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 1427 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 7175 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 268817 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 146 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 76128 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 36144 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 36 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 440 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 1492 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 226425 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 75137 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 979 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 36996 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 110644 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 46426 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 35507 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 1.392305 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 226182 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 225916 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 128242 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 134834 # num instructions consuming a value
|
|
system.cpu1.iew.wb_rate 1.389175 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.951110 # average fanout of values written-back
|
|
system.cpu1.commit.commitSquashedInsts 13383 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 5429 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 1261 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 154086 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 1.657380 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 2.063453 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 63982 41.52% 41.52% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 43006 27.91% 69.43% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 5237 3.40% 72.83% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 6258 4.06% 76.89% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 1532 0.99% 77.89% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 30979 20.11% 97.99% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 844 0.55% 98.54% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.16% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 1302 0.84% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 154086 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 255379 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 255379 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 108350 # Number of memory references committed
|
|
system.cpu1.commit.loads 73633 # Number of loads committed
|
|
system.cpu1.commit.membars 4715 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 45393 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 175866 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu1.commit.op_class_0::No_OpClass 36183 14.17% 14.17% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntAlu 106131 41.56% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.73% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemRead 78348 30.68% 86.41% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemWrite 34717 13.59% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::total 255379 # Class of committed instruction
|
|
system.cpu1.commit.bw_lim_events 1302 # number cycles where commit BW limit reached
|
|
system.cpu1.rob.rob_reads 420960 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 540023 # The number of ROB writes
|
|
system.cpu1.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 6041 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 45271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 214481 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 214481 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.cpi 0.758230 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 0.758230 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 1.318860 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 1.318860 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 391734 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 183502 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 112279 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
|
|
system.cpu1.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 25.736588 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 40830 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 1407.931034 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.736588 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050267 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.050267 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 315852 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 315852 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 43688 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 43688 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 34492 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 34492 # number of WriteReq hits
|
|
system.cpu1.dcache.SwapReq_hits::cpu1.data 17 # number of SwapReq hits
|
|
system.cpu1.dcache.SwapReq_hits::total 17 # number of SwapReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 78180 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 78180 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 78180 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 78180 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 495 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 495 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 157 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 157 # number of WriteReq misses
|
|
system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses
|
|
system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 652 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 652 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 652 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 652 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8967000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 8967000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3364000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 3364000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 599000 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::total 599000 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 12331000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 12331000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 12331000 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 12331000 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 44183 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 44183 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 34649 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 34649 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 78832 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 78832 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 78832 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 78832 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011203 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.011203 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004531 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.004531 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.750000 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::total 0.750000 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008271 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.008271 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008271 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.008271 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18115.151515 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 18115.151515 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21426.751592 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21426.751592 # average WriteReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11745.098039 # average SwapReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::total 11745.098039 # average SwapReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18912.576687 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 18912.576687 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18912.576687 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 18912.576687 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 331 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 51 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 382 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 382 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 382 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 382 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1988000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1748500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1748500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 548000 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 548000 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3736500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 3736500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3736500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 3736500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003712 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003712 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003059 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003059 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.750000 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003425 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.003425 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003425 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.003425 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12121.951220 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12121.951220 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16495.283019 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16495.283019 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10745.098039 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10745.098039 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13838.888889 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13838.888889 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13838.888889 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13838.888889 # average overall mshr miss latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 383 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 84.417280 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 20534 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 41.399194 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.417280 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164877 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.164877 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 21613 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 21613 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 20534 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 20534 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 20534 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 20534 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 20534 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 20534 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 583 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 583 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 583 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 583 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 583 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 583 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14299500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 14299500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 14299500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 14299500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 14299500 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 14299500 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 21117 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 21117 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 21117 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 21117 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 21117 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 21117 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027608 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.027608 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027608 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.027608 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027608 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.027608 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24527.444254 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 24527.444254 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24527.444254 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 24527.444254 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24527.444254 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 24527.444254 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 64 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.writebacks::writebacks 383 # number of writebacks
|
|
system.cpu1.icache.writebacks::total 383 # number of writebacks
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 87 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 87 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 87 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 87 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11785500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 11785500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11785500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 11785500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11785500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 11785500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023488 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.023488 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.023488 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23761.088710 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 23761.088710 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 23761.088710 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.branchPred.lookups 51016 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 47608 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 1273 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 43707 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 42688 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 97.668566 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 903 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
|
|
system.cpu2.numCycles 162253 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 31836 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 280333 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 51016 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 43591 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 126252 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 2703 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu2.fetch.PendingTrapStallCycles 1153 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.CacheLines 22874 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 441 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 160605 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.745481 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.165535 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 60810 37.86% 37.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 50841 31.66% 69.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 7311 4.55% 74.07% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 3498 2.18% 76.25% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 961 0.60% 76.85% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 31234 19.45% 96.30% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 1226 0.76% 97.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 786 0.49% 97.55% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 3938 2.45% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 160605 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.314423 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 1.727752 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 17488 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 62772 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 75260 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 3724 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 1351 # Number of cycles decode is squashing
|
|
system.cpu2.decode.DecodedInsts 265175 # Number of instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 1351 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 18185 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 29493 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 13900 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 76790 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 20876 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 262017 # Number of instructions processed by rename
|
|
system.cpu2.rename.IQFullEvents 18650 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
|
|
system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers
|
|
system.cpu2.rename.RenamedOperands 183428 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 498093 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 388599 # Number of integer rename lookups
|
|
system.cpu2.rename.CommittedMaps 169446 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 13982 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 1189 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 1258 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 25354 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 72684 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 33991 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 34917 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 28890 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 216663 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 7106 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 219007 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 13119 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 11098 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 160605 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 1.363637 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.376138 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 64456 40.13% 40.13% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 23625 14.71% 54.84% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 33318 20.75% 75.59% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 32915 20.49% 96.08% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 3374 2.10% 98.18% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.19% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 893 0.56% 99.74% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 160605 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 108075 49.35% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 77606 35.44% 84.78% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 33326 15.22% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 219007 # Type of FU issued
|
|
system.cpu2.iq.rate 1.349787 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.001566 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 598981 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 236927 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 217448 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 219350 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 28643 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 2671 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 1575 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 1351 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 8096 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 259522 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 72684 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 33991 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 1139 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 1062 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 217972 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 71586 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 1035 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 35753 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 104818 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 45124 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 33232 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 1.343408 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 217734 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 217448 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 122408 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 129014 # num instructions consuming a value
|
|
system.cpu2.iew.wb_rate 1.340179 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.948796 # average fanout of values written-back
|
|
system.cpu2.commit.commitSquashedInsts 13957 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 6419 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 1273 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 158015 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 1.553777 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 2.025126 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 70555 44.65% 44.65% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 41677 26.38% 71.03% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 5250 3.32% 74.35% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 7214 4.57% 78.91% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 1535 0.97% 79.89% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 28695 18.16% 98.05% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 838 0.53% 98.58% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 950 0.60% 99.18% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 1301 0.82% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 158015 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 245520 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 245520 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 102429 # Number of memory references committed
|
|
system.cpu2.commit.loads 70013 # Number of loads committed
|
|
system.cpu2.commit.membars 5702 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 44083 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 168630 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu2.commit.op_class_0::No_OpClass 34870 14.20% 14.20% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntAlu 102519 41.76% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.96% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemRead 75715 30.84% 86.80% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemWrite 32416 13.20% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::total 245520 # Class of committed instruction
|
|
system.cpu2.commit.bw_lim_events 1301 # number cycles where commit BW limit reached
|
|
system.cpu2.rob.rob_reads 415605 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 521544 # The number of ROB writes
|
|
system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 1648 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 45643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 204948 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 204948 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.cpi 0.791679 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 0.791679 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 1.263138 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 1.263138 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 374158 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 175347 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu2.misc_regfile_reads 106430 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
|
|
system.cpu2.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu2.dcache.tags.tagsinuse 23.147052 # Cycle average of tags in use
|
|
system.cpu2.dcache.tags.total_refs 38440 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.tags.avg_refs 1372.857143 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.147052 # Average occupied blocks per requestor
|
|
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045209 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_percent::total 0.045209 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
|
|
system.cpu2.dcache.tags.tag_accesses 301603 # Number of tag accesses
|
|
system.cpu2.dcache.tags.data_accesses 301603 # Number of data accesses
|
|
system.cpu2.dcache.ReadReq_hits::cpu2.data 42391 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_hits::total 42391 # number of ReadReq hits
|
|
system.cpu2.dcache.WriteReq_hits::cpu2.data 32186 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_hits::total 32186 # number of WriteReq hits
|
|
system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
|
|
system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits
|
|
system.cpu2.dcache.demand_hits::cpu2.data 74577 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_hits::total 74577 # number of demand (read+write) hits
|
|
system.cpu2.dcache.overall_hits::cpu2.data 74577 # number of overall hits
|
|
system.cpu2.dcache.overall_hits::total 74577 # number of overall hits
|
|
system.cpu2.dcache.ReadReq_misses::cpu2.data 529 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_misses::total 529 # number of ReadReq misses
|
|
system.cpu2.dcache.WriteReq_misses::cpu2.data 159 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_misses::total 159 # number of WriteReq misses
|
|
system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses
|
|
system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses
|
|
system.cpu2.dcache.demand_misses::cpu2.data 688 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_misses::total 688 # number of demand (read+write) misses
|
|
system.cpu2.dcache.overall_misses::cpu2.data 688 # number of overall misses
|
|
system.cpu2.dcache.overall_misses::total 688 # number of overall misses
|
|
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8601000 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_latency::total 8601000 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3593000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::total 3593000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 655000 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::total 655000 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::cpu2.data 12194000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::total 12194000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::cpu2.data 12194000 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::total 12194000 # number of overall miss cycles
|
|
system.cpu2.dcache.ReadReq_accesses::cpu2.data 42920 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_accesses::total 42920 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::cpu2.data 32345 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::total 32345 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.demand_accesses::cpu2.data 75265 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_accesses::total 75265 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::cpu2.data 75265 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::total 75265 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.012325 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::total 0.012325 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004916 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::total 0.004916 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.009141 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_miss_rate::total 0.009141 # miss rate for demand accesses
|
|
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.009141 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_miss_rate::total 0.009141 # miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16258.979206 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::total 16258.979206 # average ReadReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22597.484277 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::total 22597.484277 # average WriteReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11293.103448 # average SwapReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::total 11293.103448 # average SwapReq miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17723.837209 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::total 17723.837209 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17723.837209 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::total 17723.837209 # average overall miss latency
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 359 # number of ReadReq MSHR hits
|
|
system.cpu2.dcache.ReadReq_mshr_hits::total 359 # number of ReadReq MSHR hits
|
|
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 53 # number of WriteReq MSHR hits
|
|
system.cpu2.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits
|
|
system.cpu2.dcache.demand_mshr_hits::cpu2.data 412 # number of demand (read+write) MSHR hits
|
|
system.cpu2.dcache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits
|
|
system.cpu2.dcache.overall_mshr_hits::cpu2.data 412 # number of overall MSHR hits
|
|
system.cpu2.dcache.overall_mshr_hits::total 412 # number of overall MSHR hits
|
|
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::cpu2.data 276 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::cpu2.data 276 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::total 276 # number of overall MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1653000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1653000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1845000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 597000 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 597000 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3498000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::total 3498000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3498000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::total 3498000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003961 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003961 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003277 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003277 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003667 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::total 0.003667 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003667 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::total 0.003667 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9723.529412 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9723.529412 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17405.660377 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17405.660377 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10293.103448 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10293.103448 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12673.913043 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12673.913043 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12673.913043 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12673.913043 # average overall mshr miss latency
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.icache.tags.replacements 386 # number of replacements
|
|
system.cpu2.icache.tags.tagsinuse 77.661611 # Cycle average of tags in use
|
|
system.cpu2.icache.tags.total_refs 22304 # Total number of references to valid blocks.
|
|
system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.tags.avg_refs 44.608000 # Average number of references to valid blocks.
|
|
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.661611 # Average occupied blocks per requestor
|
|
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151683 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_percent::total 0.151683 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id
|
|
system.cpu2.icache.tags.tag_accesses 23374 # Number of tag accesses
|
|
system.cpu2.icache.tags.data_accesses 23374 # Number of data accesses
|
|
system.cpu2.icache.ReadReq_hits::cpu2.inst 22304 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_hits::total 22304 # number of ReadReq hits
|
|
system.cpu2.icache.demand_hits::cpu2.inst 22304 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_hits::total 22304 # number of demand (read+write) hits
|
|
system.cpu2.icache.overall_hits::cpu2.inst 22304 # number of overall hits
|
|
system.cpu2.icache.overall_hits::total 22304 # number of overall hits
|
|
system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses
|
|
system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses
|
|
system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses
|
|
system.cpu2.icache.overall_misses::total 570 # number of overall misses
|
|
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8095000 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_latency::total 8095000 # number of ReadReq miss cycles
|
|
system.cpu2.icache.demand_miss_latency::cpu2.inst 8095000 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_latency::total 8095000 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.overall_miss_latency::cpu2.inst 8095000 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_latency::total 8095000 # number of overall miss cycles
|
|
system.cpu2.icache.ReadReq_accesses::cpu2.inst 22874 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_accesses::total 22874 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.demand_accesses::cpu2.inst 22874 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_accesses::total 22874 # number of demand (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::cpu2.inst 22874 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::total 22874 # number of overall (read+write) accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024919 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::total 0.024919 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024919 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_miss_rate::total 0.024919 # miss rate for demand accesses
|
|
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024919 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_miss_rate::total 0.024919 # miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14201.754386 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::total 14201.754386 # average ReadReq miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14201.754386 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::total 14201.754386 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14201.754386 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::total 14201.754386 # average overall miss latency
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.writebacks::writebacks 386 # number of writebacks
|
|
system.cpu2.icache.writebacks::total 386 # number of writebacks
|
|
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 70 # number of ReadReq MSHR hits
|
|
system.cpu2.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
|
|
system.cpu2.icache.demand_mshr_hits::cpu2.inst 70 # number of demand (read+write) MSHR hits
|
|
system.cpu2.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
|
|
system.cpu2.icache.overall_mshr_hits::cpu2.inst 70 # number of overall MSHR hits
|
|
system.cpu2.icache.overall_mshr_hits::total 70 # number of overall MSHR hits
|
|
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7049500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::total 7049500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7049500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::total 7049500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7049500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::total 7049500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021859 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::total 0.021859 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::total 0.021859 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14099 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 14099 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14099 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::total 14099 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14099 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::total 14099 # average overall mshr miss latency
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.branchPred.lookups 49230 # Number of BP lookups
|
|
system.cpu3.branchPred.condPredicted 45728 # Number of conditional branches predicted
|
|
system.cpu3.branchPred.condIncorrect 1271 # Number of conditional branches incorrect
|
|
system.cpu3.branchPred.BTBLookups 41796 # Number of BTB lookups
|
|
system.cpu3.branchPred.BTBHits 40803 # Number of BTB hits
|
|
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu3.branchPred.BTBHitPct 97.624175 # BTB Hit Percentage
|
|
system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target.
|
|
system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
|
|
system.cpu3.numCycles 161890 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.fetch.icacheStallCycles 32992 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu3.fetch.Insts 268412 # Number of instructions fetch has processed
|
|
system.cpu3.fetch.Branches 49230 # Number of branches that fetch encountered
|
|
system.cpu3.fetch.predictedBranches 41709 # Number of branches that fetch has predicted taken
|
|
system.cpu3.fetch.Cycles 124419 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu3.fetch.SquashCycles 2697 # Number of cycles fetch has spent squashing
|
|
system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps
|
|
system.cpu3.fetch.CacheLines 24017 # Number of cache lines fetched
|
|
system.cpu3.fetch.IcacheSquashes 451 # Number of outstanding Icache misses that were squashed
|
|
system.cpu3.fetch.rateDist::samples 159937 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::mean 1.678236 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::stdev 2.146445 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::0 63357 39.61% 39.61% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::1 49486 30.94% 70.55% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::2 7847 4.91% 75.46% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::3 3455 2.16% 77.62% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::4 942 0.59% 78.21% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::5 28830 18.03% 96.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::6 1207 0.75% 96.99% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::7 797 0.50% 97.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::8 4016 2.51% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::total 159937 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.branchRate 0.304095 # Number of branch fetches per cycle
|
|
system.cpu3.fetch.rate 1.657990 # Number of inst fetches per cycle
|
|
system.cpu3.decode.IdleCycles 17620 # Number of cycles decode is idle
|
|
system.cpu3.decode.BlockedCycles 66098 # Number of cycles decode is blocked
|
|
system.cpu3.decode.RunCycles 70935 # Number of cycles decode is running
|
|
system.cpu3.decode.UnblockCycles 3926 # Number of cycles decode is unblocking
|
|
system.cpu3.decode.SquashCycles 1348 # Number of cycles decode is squashing
|
|
system.cpu3.decode.DecodedInsts 252986 # Number of instructions handled by decode
|
|
system.cpu3.rename.SquashCycles 1348 # Number of cycles rename is squashing
|
|
system.cpu3.rename.IdleCycles 18323 # Number of cycles rename is idle
|
|
system.cpu3.rename.BlockCycles 31370 # Number of cycles rename is blocking
|
|
system.cpu3.rename.serializeStallCycles 13970 # count of cycles rename stalled for serializing inst
|
|
system.cpu3.rename.RunCycles 72885 # Number of cycles rename is running
|
|
system.cpu3.rename.UnblockCycles 22031 # Number of cycles rename is unblocking
|
|
system.cpu3.rename.RenamedInsts 249675 # Number of instructions processed by rename
|
|
system.cpu3.rename.IQFullEvents 20026 # Number of times rename has blocked due to IQ full
|
|
system.cpu3.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full
|
|
system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers
|
|
system.cpu3.rename.RenamedOperands 174506 # Number of destination operands rename has renamed
|
|
system.cpu3.rename.RenameLookups 471658 # Number of register rename lookups that rename has made
|
|
system.cpu3.rename.int_rename_lookups 368736 # Number of integer rename lookups
|
|
system.cpu3.rename.CommittedMaps 160859 # Number of HB maps that are committed
|
|
system.cpu3.rename.UndoneMaps 13647 # Number of HB maps that are undone due to squashing
|
|
system.cpu3.rename.serializingInsts 1202 # count of serializing insts renamed
|
|
system.cpu3.rename.tempSerializingInsts 1275 # count of temporary serializing insts renamed
|
|
system.cpu3.rename.skidInsts 26657 # count of insts added to the skid buffer
|
|
system.cpu3.memDep0.insertedLoads 68456 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.insertedStores 31644 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.conflictingLoads 33001 # Number of conflicting loads.
|
|
system.cpu3.memDep0.conflictingStores 26549 # Number of conflicting stores.
|
|
system.cpu3.iq.iqInstsAdded 205848 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu3.iq.iqNonSpecInstsAdded 7559 # Number of non-speculative instructions added to the IQ
|
|
system.cpu3.iq.iqInstsIssued 208921 # Number of instructions issued
|
|
system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued
|
|
system.cpu3.iq.iqSquashedInstsExamined 12739 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu3.iq.iqSquashedOperandsExamined 10220 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu3.iq.iqSquashedNonSpecRemoved 712 # Number of squashed non-spec instructions that were removed
|
|
system.cpu3.iq.issued_per_cycle::samples 159937 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::mean 1.306271 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::stdev 1.372225 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::0 67005 41.89% 41.89% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::1 24940 15.59% 57.49% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::2 31075 19.43% 76.92% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::3 30637 19.16% 96.07% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::4 3376 2.11% 98.18% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::5 1620 1.01% 99.20% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::6 871 0.54% 99.74% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::7 214 0.13% 99.88% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::total 159937 # Number of insts issued each cycle
|
|
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntAlu 82 24.70% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntMult 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.70% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::MemRead 41 12.35% 37.05% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::MemWrite 209 62.95% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntAlu 103999 49.78% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::MemRead 73864 35.35% 85.13% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::MemWrite 31058 14.87% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::total 208921 # Type of FU issued
|
|
system.cpu3.iq.rate 1.290512 # Inst issue rate
|
|
system.cpu3.iq.fu_busy_cnt 332 # FU busy when requested
|
|
system.cpu3.iq.fu_busy_rate 0.001589 # FU busy rate (busy events/executed inst)
|
|
system.cpu3.iq.int_inst_queue_reads 578115 # Number of integer instruction queue reads
|
|
system.cpu3.iq.int_inst_queue_writes 226182 # Number of integer instruction queue writes
|
|
system.cpu3.iq.int_inst_queue_wakeup_accesses 207437 # Number of integer instruction queue wakeup accesses
|
|
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu3.iq.int_alu_accesses 209253 # Number of integer alu accesses
|
|
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu3.iew.lsq.thread0.forwLoads 26373 # Number of loads that had data forwarded from stores
|
|
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed
|
|
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu3.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations
|
|
system.cpu3.iew.lsq.thread0.squashedStores 1480 # Number of stores squashed
|
|
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu3.iew.iewSquashCycles 1348 # Number of cycles IEW is squashing
|
|
system.cpu3.iew.iewBlockCycles 8395 # Number of cycles IEW is blocking
|
|
system.cpu3.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking
|
|
system.cpu3.iew.iewDispatchedInsts 247262 # Number of instructions dispatched to IQ
|
|
system.cpu3.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch
|
|
system.cpu3.iew.iewDispLoadInsts 68456 # Number of dispatched load instructions
|
|
system.cpu3.iew.iewDispStoreInsts 31644 # Number of dispatched store instructions
|
|
system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions
|
|
system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall
|
|
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu3.iew.memOrderViolationEvents 36 # Number of memory order violations
|
|
system.cpu3.iew.predictedTakenIncorrect 438 # Number of branches that were predicted taken incorrectly
|
|
system.cpu3.iew.predictedNotTakenIncorrect 1065 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute
|
|
system.cpu3.iew.iewExecutedInsts 207928 # Number of executed instructions
|
|
system.cpu3.iew.iewExecLoadInsts 67431 # Number of load instructions executed
|
|
system.cpu3.iew.iewExecSquashedInsts 993 # Number of squashed instructions skipped in execute
|
|
system.cpu3.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu3.iew.exec_nop 33855 # number of nop insts executed
|
|
system.cpu3.iew.exec_refs 98404 # number of memory reference insts executed
|
|
system.cpu3.iew.exec_branches 43312 # Number of branches executed
|
|
system.cpu3.iew.exec_stores 30973 # Number of stores executed
|
|
system.cpu3.iew.exec_rate 1.284378 # Inst execution rate
|
|
system.cpu3.iew.wb_sent 207701 # cumulative count of insts sent to commit
|
|
system.cpu3.iew.wb_count 207437 # cumulative count of insts written-back
|
|
system.cpu3.iew.wb_producers 116002 # num instructions producing a value
|
|
system.cpu3.iew.wb_consumers 122598 # num instructions consuming a value
|
|
system.cpu3.iew.wb_rate 1.281345 # insts written-back per cycle
|
|
system.cpu3.iew.wb_fanout 0.946198 # average fanout of values written-back
|
|
system.cpu3.commit.commitSquashedInsts 13505 # The number of squashed insts skipped by commit
|
|
system.cpu3.commit.commitNonSpecStalls 6847 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu3.commit.branchMispredicts 1271 # The number of times a branch was mispredicted
|
|
system.cpu3.commit.committed_per_cycle::samples 157409 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::mean 1.484744 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::stdev 1.997930 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::0 73609 46.76% 46.76% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::1 39844 25.31% 72.08% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::2 5242 3.33% 75.41% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::3 7652 4.86% 80.27% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::4 1542 0.98% 81.25% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::5 26417 16.78% 98.03% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::6 849 0.54% 98.57% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::7 951 0.60% 99.17% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::8 1303 0.83% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::total 157409 # Number of insts commited each cycle
|
|
system.cpu3.commit.committedInsts 233712 # Number of instructions committed
|
|
system.cpu3.commit.committedOps 233712 # Number of ops (including micro ops) committed
|
|
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu3.commit.refs 96099 # Number of memory references committed
|
|
system.cpu3.commit.loads 65935 # Number of loads committed
|
|
system.cpu3.commit.membars 6131 # Number of memory barriers committed
|
|
system.cpu3.commit.branches 42256 # Number of branches committed
|
|
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu3.commit.int_insts 160475 # Number of committed integer instructions.
|
|
system.cpu3.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu3.commit.op_class_0::No_OpClass 33044 14.14% 14.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IntAlu 98438 42.12% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.26% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::MemRead 72066 30.84% 87.09% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::MemWrite 30164 12.91% 100.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::total 233712 # Class of committed instruction
|
|
system.cpu3.commit.bw_lim_events 1303 # number cycles where commit BW limit reached
|
|
system.cpu3.rob.rob_reads 402737 # The number of ROB reads
|
|
system.cpu3.rob.rob_writes 496962 # The number of ROB writes
|
|
system.cpu3.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu3.idleCycles 1953 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu3.quiesceCycles 46007 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu3.committedInsts 194537 # Number of Instructions Simulated
|
|
system.cpu3.committedOps 194537 # Number of Ops (including micro ops) Simulated
|
|
system.cpu3.cpi 0.832181 # CPI: Cycles Per Instruction
|
|
system.cpu3.cpi_total 0.832181 # CPI: Total CPI of All Threads
|
|
system.cpu3.ipc 1.201662 # IPC: Instructions Per Cycle
|
|
system.cpu3.ipc_total 1.201662 # IPC: Total IPC of All Threads
|
|
system.cpu3.int_regfile_reads 355006 # number of integer regfile reads
|
|
system.cpu3.int_regfile_writes 166699 # number of integer regfile writes
|
|
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu3.misc_regfile_reads 100037 # number of misc regfile reads
|
|
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
|
|
system.cpu3.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu3.dcache.tags.tagsinuse 24.251319 # Cycle average of tags in use
|
|
system.cpu3.dcache.tags.total_refs 36167 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.tags.avg_refs 1291.678571 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.251319 # Average occupied blocks per requestor
|
|
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047366 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_percent::total 0.047366 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
|
|
system.cpu3.dcache.tags.tag_accesses 285043 # Number of tag accesses
|
|
system.cpu3.dcache.tags.data_accesses 285043 # Number of data accesses
|
|
system.cpu3.dcache.ReadReq_hits::cpu3.data 40546 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_hits::total 40546 # number of ReadReq hits
|
|
system.cpu3.dcache.WriteReq_hits::cpu3.data 29945 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_hits::total 29945 # number of WriteReq hits
|
|
system.cpu3.dcache.SwapReq_hits::cpu3.data 17 # number of SwapReq hits
|
|
system.cpu3.dcache.SwapReq_hits::total 17 # number of SwapReq hits
|
|
system.cpu3.dcache.demand_hits::cpu3.data 70491 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_hits::total 70491 # number of demand (read+write) hits
|
|
system.cpu3.dcache.overall_hits::cpu3.data 70491 # number of overall hits
|
|
system.cpu3.dcache.overall_hits::total 70491 # number of overall hits
|
|
system.cpu3.dcache.ReadReq_misses::cpu3.data 489 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_misses::total 489 # number of ReadReq misses
|
|
system.cpu3.dcache.WriteReq_misses::cpu3.data 149 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_misses::total 149 # number of WriteReq misses
|
|
system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses
|
|
system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses
|
|
system.cpu3.dcache.demand_misses::cpu3.data 638 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_misses::total 638 # number of demand (read+write) misses
|
|
system.cpu3.dcache.overall_misses::cpu3.data 638 # number of overall misses
|
|
system.cpu3.dcache.overall_misses::total 638 # number of overall misses
|
|
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8138500 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_latency::total 8138500 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3781500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::total 3781500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 606500 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::total 606500 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::cpu3.data 11920000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::total 11920000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::cpu3.data 11920000 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::total 11920000 # number of overall miss cycles
|
|
system.cpu3.dcache.ReadReq_accesses::cpu3.data 41035 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_accesses::total 41035 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::cpu3.data 30094 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::total 30094 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.demand_accesses::cpu3.data 71129 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_accesses::total 71129 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::cpu3.data 71129 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::total 71129 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011917 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::total 0.011917 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004951 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::total 0.004951 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.757143 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::total 0.757143 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008970 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_miss_rate::total 0.008970 # miss rate for demand accesses
|
|
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008970 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_miss_rate::total 0.008970 # miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16643.149284 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::total 16643.149284 # average ReadReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25379.194631 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::total 25379.194631 # average WriteReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11443.396226 # average SwapReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::total 11443.396226 # average SwapReq miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18683.385580 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::total 18683.385580 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18683.385580 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::total 18683.385580 # average overall miss latency
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 328 # number of ReadReq MSHR hits
|
|
system.cpu3.dcache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits
|
|
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 46 # number of WriteReq MSHR hits
|
|
system.cpu3.dcache.WriteReq_mshr_hits::total 46 # number of WriteReq MSHR hits
|
|
system.cpu3.dcache.demand_mshr_hits::cpu3.data 374 # number of demand (read+write) MSHR hits
|
|
system.cpu3.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits
|
|
system.cpu3.dcache.overall_mshr_hits::cpu3.data 374 # number of overall MSHR hits
|
|
system.cpu3.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits
|
|
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1609000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1609000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2139500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2139500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 553500 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 553500 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3748500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::total 3748500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3748500 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::total 3748500 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003923 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003923 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003423 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003423 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.757143 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.757143 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::total 0.003712 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::total 0.003712 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9993.788820 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9993.788820 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 20771.844660 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 20771.844660 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10443.396226 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10443.396226 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14198.863636 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14198.863636 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14198.863636 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14198.863636 # average overall mshr miss latency
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.icache.tags.replacements 384 # number of replacements
|
|
system.cpu3.icache.tags.tagsinuse 80.879647 # Cycle average of tags in use
|
|
system.cpu3.icache.tags.total_refs 23443 # Total number of references to valid blocks.
|
|
system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.tags.avg_refs 47.074297 # Average number of references to valid blocks.
|
|
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.879647 # Average occupied blocks per requestor
|
|
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157968 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_percent::total 0.157968 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id
|
|
system.cpu3.icache.tags.tag_accesses 24515 # Number of tag accesses
|
|
system.cpu3.icache.tags.data_accesses 24515 # Number of data accesses
|
|
system.cpu3.icache.ReadReq_hits::cpu3.inst 23443 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_hits::total 23443 # number of ReadReq hits
|
|
system.cpu3.icache.demand_hits::cpu3.inst 23443 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_hits::total 23443 # number of demand (read+write) hits
|
|
system.cpu3.icache.overall_hits::cpu3.inst 23443 # number of overall hits
|
|
system.cpu3.icache.overall_hits::total 23443 # number of overall hits
|
|
system.cpu3.icache.ReadReq_misses::cpu3.inst 574 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_misses::total 574 # number of ReadReq misses
|
|
system.cpu3.icache.demand_misses::cpu3.inst 574 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_misses::total 574 # number of demand (read+write) misses
|
|
system.cpu3.icache.overall_misses::cpu3.inst 574 # number of overall misses
|
|
system.cpu3.icache.overall_misses::total 574 # number of overall misses
|
|
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7717500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_latency::total 7717500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.demand_miss_latency::cpu3.inst 7717500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_latency::total 7717500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.overall_miss_latency::cpu3.inst 7717500 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_latency::total 7717500 # number of overall miss cycles
|
|
system.cpu3.icache.ReadReq_accesses::cpu3.inst 24017 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_accesses::total 24017 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.demand_accesses::cpu3.inst 24017 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_accesses::total 24017 # number of demand (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::cpu3.inst 24017 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::total 24017 # number of overall (read+write) accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023900 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::total 0.023900 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023900 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_miss_rate::total 0.023900 # miss rate for demand accesses
|
|
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023900 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_miss_rate::total 0.023900 # miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13445.121951 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::total 13445.121951 # average ReadReq miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13445.121951 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::total 13445.121951 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13445.121951 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::total 13445.121951 # average overall miss latency
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.writebacks::writebacks 384 # number of writebacks
|
|
system.cpu3.icache.writebacks::total 384 # number of writebacks
|
|
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 76 # number of ReadReq MSHR hits
|
|
system.cpu3.icache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits
|
|
system.cpu3.icache.demand_mshr_hits::cpu3.inst 76 # number of demand (read+write) MSHR hits
|
|
system.cpu3.icache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits
|
|
system.cpu3.icache.overall_mshr_hits::cpu3.inst 76 # number of overall MSHR hits
|
|
system.cpu3.icache.overall_mshr_hits::total 76 # number of overall MSHR hits
|
|
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6640500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::total 6640500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6640500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::total 6640500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6640500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::total 6640500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020735 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::total 0.020735 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::total 0.020735 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13334.337349 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13334.337349 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13334.337349 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::total 13334.337349 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13334.337349 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::total 13334.337349 # average overall mshr miss latency
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 0 # number of replacements
|
|
system.l2c.tags.tagsinuse 419.138543 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 2347 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 532 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 4.411654 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 0.788194 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 288.006073 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 58.075910 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 61.760427 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 5.322052 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 2.559109 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 0.677187 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.inst 1.231634 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.data 0.717957 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.004395 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.000886 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.000942 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.000039 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.inst 0.000019 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.006396 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 25618 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 25618 # Number of data accesses
|
|
system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
|
|
system.l2c.WritebackClean_hits::writebacks 676 # number of WritebackClean hits
|
|
system.l2c.WritebackClean_hits::total 676 # number of WritebackClean hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 246 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 410 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu2.inst 489 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu3.inst 493 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 1638 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.inst 246 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 410 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 489 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 493 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1670 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 246 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 410 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 489 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 11 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 493 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
|
|
system.l2c.overall_hits::total 1670 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 27 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu3.data 22 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 89 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 362 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 86 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu2.inst 11 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu3.inst 5 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 464 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.inst 362 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 86 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 11 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 679 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 362 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 169 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 86 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 11 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 5 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
|
|
system.l2c.overall_misses::total 679 # number of overall misses
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 7622500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 1059000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 1210000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3.data 1404500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 11296000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 27679500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6438500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 788500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu3.inst 341500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 35248000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 5981500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 540000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu2.data 82500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu3.data 96500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 6700500 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 27679500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 13604000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 6438500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1599000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 788500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 1292500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.inst 341500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.data 1501000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 53244500 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 27679500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 13604000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 6438500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1599000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 788500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 1292500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.inst 341500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.data 1501000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 53244500 # number of overall miss cycles
|
|
system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::writebacks 676 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::total 676 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 608 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 496 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu2.inst 500 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu3.inst 498 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 2102 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 80 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 12 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu2.data 12 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu3.data 12 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 116 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 608 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 496 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 500 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.inst 498 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2349 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 608 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 496 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 500 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2349 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.900000 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.967391 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.595395 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173387 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.022000 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010040 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.220742 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.595395 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.173387 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.022000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.inst 0.010040 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.289059 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.595395 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.173387 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.022000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.inst 0.010040 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.289059 # miss rate for overall accesses
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81090.425532 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81461.538462 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 100833.333333 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 117041.666667 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 86229.007634 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76462.707182 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74866.279070 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 71681.818182 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 68300 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 75965.517241 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 79753.333333 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 77142.857143 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82500 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 96500 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 79767.857143 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 76462.707182 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 80497.041420 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 74866.279070 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 79950 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 71681.818182 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 99423.076923 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.inst 68300 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.data 115461.538462 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 78416.053019 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 76462.707182 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 80497.041420 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 74866.279070 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 79950 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 71681.818182 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 99423.076923 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.inst 68300 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.data 115461.538462 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 78416.053019 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 5 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 3 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 27 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 21 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu3.data 22 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 89 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 361 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 82 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 6 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 2 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 451 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 75 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 7 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 1 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 84 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 361 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 82 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 6 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.inst 2 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 666 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 361 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 82 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 6 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.inst 2 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 666 # number of overall MSHR misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 512500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 359500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 401500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 416000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 1689500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6682500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 929000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1090000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1284500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 9986000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 23889000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5419500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 436500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 145500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 29890500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5231500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 470000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 72500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 86500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 5860500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 23889000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 11914000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 5419500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 1399000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 436500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 1162500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.inst 145500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.data 1371000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 45737000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 23889000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 11914000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 5419500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 1399000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 436500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 1162500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.inst 145500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.data 1371000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 45737000 # number of overall MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.900000 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.967391 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18981.481481 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18921.052632 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19119.047619 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18909.090909 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18983.146067 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71090.425532 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 90833.333333 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 107041.666667 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 76229.007634 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72750 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72750 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66276.053215 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69753.333333 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67142.857143 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69767.857143 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70497.041420 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72750 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89423.076923 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72750 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105461.538462 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 68674.174174 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70497.041420 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72750 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89423.076923 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72750 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105461.538462 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 68674.174174 # average overall mshr miss latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadResp 534 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 291 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 159 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 131 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1650 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1650 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 230 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 985 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 985 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 985 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 928501 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 3534750 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 3.3 # Layer utilization (%)
|
|
system.toL2Bus.snoop_filter.tot_requests 4931 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 1335 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 2366 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadResp 2779 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackClean 1468 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 294 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 294 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 387 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 387 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 678 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1530 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 593 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1375 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1386 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 379 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1380 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 7371 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 59008 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 56256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 56704 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 244288 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 1020 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 3461 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 1.293268 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 1.185819 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 1230 35.54% 35.54% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 830 23.98% 59.52% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 557 16.09% 75.61% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 844 24.39% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 3461 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 3950967 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 911498 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 505495 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 746494 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 429965 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
|
|
system.toL2Bus.respLayer4.occupancy 752493 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%)
|
|
system.toL2Bus.respLayer5.occupancy 440466 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
|
|
system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%)
|
|
system.toL2Bus.respLayer7.occupancy 422962 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|