312 lines
9.9 KiB
C++
312 lines
9.9 KiB
C++
/* $Id$ */
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/* @file
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* Tsunami CChip (processor, memory, or IO)
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "dev/console.hh"
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#include "dev/tsunami_cchip.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "cpu/intr_control.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t,
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Addr addr, Addr mask, MemoryController *mmu)
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: MmapDevice(name, addr, mask, mmu), tsunami(t)
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{
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for(int i=0; i < Tsunami::Max_CPUs; i++) {
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dim[i] = 0;
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dir[i] = 0;
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dirInterrupting[i] = false;
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}
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drir = 0;
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misc = 0;
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RTCInterrupting = false;
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//Put back pointer in tsunami
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tsunami->cchip = this;
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}
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Fault
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TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
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{
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DPRINTF(Tsunami, "read va=%#x size=%d\n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr & addr_mask) >> 6;
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ExecContext *xc = req->xc;
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switch (req->size) {
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_CC_CSR:
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*(uint64_t*)data = 0x0;
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return No_Fault;
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case TSDEV_CC_MTR:
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panic("TSDEV_CC_MTR not implemeted\n");
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return No_Fault;
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case TSDEV_CC_MISC:
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*(uint64_t*)data = misc | (xc->cpu_id & 0x3);
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return No_Fault;
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case TSDEV_CC_AAR0:
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case TSDEV_CC_AAR1:
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case TSDEV_CC_AAR2:
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case TSDEV_CC_AAR3:
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panic("TSDEV_CC_AARx not implemeted\n");
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return No_Fault;
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case TSDEV_CC_DIM0:
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*(uint64_t*)data = dim[0];
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return No_Fault;
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case TSDEV_CC_DIM1:
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*(uint64_t*)data = dim[1];
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return No_Fault;
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case TSDEV_CC_DIM2:
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*(uint64_t*)data = dim[2];
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return No_Fault;
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case TSDEV_CC_DIM3:
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*(uint64_t*)data = dim[3];
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return No_Fault;
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case TSDEV_CC_DIR0:
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*(uint64_t*)data = dir[0];
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return No_Fault;
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case TSDEV_CC_DIR1:
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*(uint64_t*)data = dir[1];
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return No_Fault;
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case TSDEV_CC_DIR2:
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*(uint64_t*)data = dir[2];
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return No_Fault;
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case TSDEV_CC_DIR3:
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*(uint64_t*)data = dir[3];
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return No_Fault;
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case TSDEV_CC_DRIR:
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*(uint64_t*)data = drir;
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return No_Fault;
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case TSDEV_CC_PRBEN:
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panic("TSDEV_CC_PRBEN not implemented\n");
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return No_Fault;
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case TSDEV_CC_IIC0:
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case TSDEV_CC_IIC1:
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case TSDEV_CC_IIC2:
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case TSDEV_CC_IIC3:
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panic("TSDEV_CC_IICx not implemented\n");
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return No_Fault;
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case TSDEV_CC_MPR0:
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case TSDEV_CC_MPR1:
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case TSDEV_CC_MPR2:
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case TSDEV_CC_MPR3:
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panic("TSDEV_CC_MPRx not implemented\n");
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return No_Fault;
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default:
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panic("default in cchip read reached, accessing 0x%x\n");
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} // uint64_t
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n");
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}
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DPRINTFN("Tsunami CChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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Fault
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TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
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{
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DPRINTF(Tsunami, "write - va=%#x size=%d \n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr & addr_mask) >> 6;
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switch (req->size) {
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_CC_CSR:
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panic("TSDEV_CC_CSR write\n");
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return No_Fault;
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case TSDEV_CC_MTR:
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panic("TSDEV_CC_MTR write not implemented\n");
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return No_Fault;
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case TSDEV_CC_MISC:
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//If it is the seventh bit, clear the RTC interrupt
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if ((*(uint64_t*) data) & (1<<4)) {
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RTCInterrupting = false;
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tsunami->intrctrl->clear(0, TheISA::INTLEVEL_IRQ2, 0);
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DPRINTF(Tsunami, "clearing rtc interrupt\n");
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misc &= ~(1<<4);
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} else panic("TSDEV_CC_MISC write not implemented\n");
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return No_Fault;
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case TSDEV_CC_AAR0:
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case TSDEV_CC_AAR1:
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case TSDEV_CC_AAR2:
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case TSDEV_CC_AAR3:
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panic("TSDEV_CC_AARx write not implemeted\n");
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return No_Fault;
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case TSDEV_CC_DIM0:
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dim[0] = *(uint64_t*)data;
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if (dim[0] & drir) {
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dir[0] = dim[0] & drir;
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if (!dirInterrupting[0]) {
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dirInterrupting[0] = true;
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tsunami->intrctrl->post(0, TheISA::INTLEVEL_IRQ1, 0);
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DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
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}
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}
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return No_Fault;
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case TSDEV_CC_DIM1:
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dim[1] = *(uint64_t*)data;
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if (dim[1] & drir) {
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dir[1] = dim[1] & drir;
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if (!dirInterrupting[1]) {
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dirInterrupting[1] = true;
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tsunami->intrctrl->post(1, TheISA::INTLEVEL_IRQ1, 0);
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DPRINTF(Tsunami, "posting dir interrupt to cpu 1\n");
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}
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}
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return No_Fault;
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case TSDEV_CC_DIM2:
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dim[2] = *(uint64_t*)data;
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if (dim[2] & drir) {
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dir[2] = dim[2] & drir;
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if (!dirInterrupting[2]) {
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dirInterrupting[2] = true;
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tsunami->intrctrl->post(2, TheISA::INTLEVEL_IRQ1, 0);
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DPRINTF(Tsunami, "posting dir interrupt to cpu 2\n");
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}
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}
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return No_Fault;
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case TSDEV_CC_DIM3:
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dim[3] = *(uint64_t*)data;
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if ((dim[3] & drir) /*And Not Already Int*/) {
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dir[3] = dim[3] & drir;
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if (!dirInterrupting[3]) {
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dirInterrupting[3] = true;
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tsunami->intrctrl->post(3, TheISA::INTLEVEL_IRQ1, 0);
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DPRINTF(Tsunami, "posting dir interrupt to cpu 3\n");
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}
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}
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return No_Fault;
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case TSDEV_CC_DIR0:
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case TSDEV_CC_DIR1:
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case TSDEV_CC_DIR2:
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case TSDEV_CC_DIR3:
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panic("TSDEV_CC_DIR write not implemented\n");
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return No_Fault;
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case TSDEV_CC_DRIR:
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panic("TSDEV_CC_DRIR write not implemented\n");
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return No_Fault;
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case TSDEV_CC_PRBEN:
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panic("TSDEV_CC_PRBEN write not implemented\n");
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return No_Fault;
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case TSDEV_CC_IIC0:
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case TSDEV_CC_IIC1:
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case TSDEV_CC_IIC2:
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case TSDEV_CC_IIC3:
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panic("TSDEV_CC_IICx write not implemented\n");
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return No_Fault;
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case TSDEV_CC_MPR0:
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case TSDEV_CC_MPR1:
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case TSDEV_CC_MPR2:
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case TSDEV_CC_MPR3:
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panic("TSDEV_CC_MPRx write not implemented\n");
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return No_Fault;
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default:
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panic("default in cchip read reached, accessing 0x%x\n");
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}
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n");
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}
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DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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void
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TsunamiCChip::postDRIR(uint64_t bitvector)
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{
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drir |= bitvector;
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for(int i=0; i < Tsunami::Max_CPUs; i++) {
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if (bitvector & dim[i]) {
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dir[i] |= bitvector;
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if (!dirInterrupting[i]) {
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dirInterrupting[i] = true;
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tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, 0);
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DPRINTF(Tsunami, "posting dir interrupt to cpu %d\n",i);
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}
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}
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}
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}
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void
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TsunamiCChip::clearDRIR(uint64_t bitvector)
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{
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drir &= ~bitvector;
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for(int i=0; i < Tsunami::Max_CPUs; i++) {
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dir[i] &= ~bitvector;
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if (!dir[i]) {
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dirInterrupting[i] = false;
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tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, 0);
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DPRINTF(Tsunami, "clearing dir interrupt to cpu %d\n", i);
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}
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}
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}
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void
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TsunamiCChip::serialize(std::ostream &os)
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{
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// code should be written
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}
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void
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TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion)
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{
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//code should be written
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
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SimObjectParam<Tsunami *> tsunami;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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Param<Addr> mask;
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END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
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BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
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INIT_PARAM(tsunami, "Tsunami"),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(mask, "Address Mask")
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END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
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CREATE_SIM_OBJECT(TsunamiCChip)
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{
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return new TsunamiCChip(getInstanceName(), tsunami, addr, mask, mmu);
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}
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REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
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