gem5/src/arch/sparc/isa
2006-10-25 17:54:14 -04:00
..
formats Move around more SPARC memory code, and make block memory operations work with the timing cpu 2006-10-23 11:17:15 -04:00
base.isa Made sure the constructor for insts use ExtMachInst rather than MachInst, since otherwise the EXT_ASI field is lost. 2006-10-16 15:52:14 -04:00
bitfields.isa Fixed the bitfield FCN to include the right bits. 2006-10-25 17:50:39 -04:00
decoder.isa Implemented the saved and restored instructions, fixed up register window instructions so that the cwp is modified at the correct time (when handling the fault), and fixed the "done" instruction. 2006-10-25 17:54:14 -04:00
includes.isa Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description. 2006-10-23 07:55:52 -04:00
main.isa Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description. 2006-10-23 07:55:52 -04:00
operands.isa Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description. 2006-10-23 07:55:52 -04:00