gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
Steve Reinhardt 10e6450120 test: update stats
Update stats for recent changes.  Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
2013-10-16 10:44:12 -04:00

62 lines
4.7 KiB
Text

Profiler Stats
--------------
Ruby_current_time: 121759
Ruby_start_time: 0
Ruby_cycles: 121759
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8853 average: 1 | standard deviation: 0 | 0 8853 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
latency: [binsize: 8 max: 125 count: 8852 average: 12.755 | standard deviation: 22.8655 | 7475 0 0 0 0 0 0 329 974 3 3 66 1 0 0 1 ]
latency: LD: [binsize: 8 max: 101 count: 1045 average: 33.0842 | standard deviation: 31.8534 | 546 0 0 0 0 0 0 105 359 2 1 31 1 ]
latency: ST: [binsize: 8 max: 92 count: 935 average: 20.0845 | standard deviation: 28.1878 | 681 0 0 0 0 0 0 62 177 0 1 14 ]
latency: IFETCH: [binsize: 8 max: 125 count: 6864 average: 8.6639 | standard deviation: 18.0088 | 6241 0 0 0 0 0 0 162 437 1 1 21 0 0 0 1 ]
latency: RMW_Read: [binsize: 4 max: 65 count: 8 average: 10.75 | standard deviation: 21.9219 | 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
hit latency: [binsize: 1 max: 3 count: 7475 average: 3 | standard deviation: 0 | 0 0 0 7475 ]
hit latency: LD: [binsize: 1 max: 3 count: 546 average: 3 | standard deviation: 0 | 0 0 0 546 ]
hit latency: ST: [binsize: 1 max: 3 count: 681 average: 3 | standard deviation: 0 | 0 0 0 681 ]
hit latency: IFETCH: [binsize: 1 max: 3 count: 6241 average: 3 | standard deviation: 0 | 0 0 0 6241 ]
hit latency: RMW_Read: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ]
miss latency: [binsize: 8 max: 125 count: 1377 average: 65.7095 | standard deviation: 6.31582 | 0 0 0 0 0 0 0 329 974 3 3 66 1 0 0 1 ]
miss latency: LD: [binsize: 8 max: 101 count: 499 average: 66.002 | standard deviation: 7.00186 | 0 0 0 0 0 0 0 105 359 2 1 31 1 ]
miss latency: ST: [binsize: 8 max: 92 count: 254 average: 65.8898 | standard deviation: 6.41669 | 0 0 0 0 0 0 0 62 177 0 1 14 ]
miss latency: IFETCH: [binsize: 8 max: 125 count: 623 average: 65.4029 | standard deviation: 5.66282 | 0 0 0 0 0 0 0 162 437 1 1 21 0 0 0 1 ]
miss latency: RMW_Read: [binsize: 4 max: 65 count: 1 average: 65 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss latency: Directory: [binsize: 8 max: 125 count: 1377 average: 65.7095 | standard deviation: 6.31582 | 0 0 0 0 0 0 0 329 974 3 3 66 1 0 0 1 ]
miss latency: Directory::issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss latency: Directory::initial_to_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss latency: Directory::forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss latency: Directory::first_response_to_completion: [binsize: 4 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
incomplete times: 1376
miss latency: LD: Directory: [binsize: 8 max: 101 count: 499 average: 66.002 | standard deviation: 7.00186 | 0 0 0 0 0 0 0 105 359 2 1 31 1 ]
miss latency: ST: Directory: [binsize: 8 max: 92 count: 254 average: 65.8898 | standard deviation: 6.41669 | 0 0 0 0 0 0 0 62 177 0 1 14 ]
miss latency: IFETCH: Directory: [binsize: 8 max: 125 count: 623 average: 65.4029 | standard deviation: 5.66282 | 0 0 0 0 0 0 0 162 437 1 1 21 0 0 0 1 ]
miss latency: RMW_Read: Directory: [binsize: 4 max: 65 count: 1 average: 65 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
Request vs. RubySystem State Profile
--------------------------------
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 0 count: 2750 average: 0 | standard deviation: 0 | 2750 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1377 average: 0 | standard deviation: 0 | 1377 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1373 average: 0 | standard deviation: 0 | 1373 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]