902 lines
102 KiB
Plaintext
902 lines
102 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 5.139621 # Number of seconds simulated
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sim_ticks 5139621012500 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 264330 # Simulator instruction rate (inst/s)
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host_tick_rate 1617420466 # Simulator tick rate (ticks/s)
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host_mem_usage 409996 # Number of bytes of host memory used
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host_seconds 3177.67 # Real time elapsed on the host
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sim_insts 839951837 # Number of instructions simulated
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system.l2c.replacements 170440 # number of replacements
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system.l2c.tagsinuse 38394.915319 # Cycle average of tags in use
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system.l2c.total_refs 3798996 # Total number of references to valid blocks.
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system.l2c.sampled_refs 206462 # Sample count of references to valid blocks.
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system.l2c.avg_refs 18.400461 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::0 11966.871938 # Average occupied blocks per context
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system.l2c.occ_blocks::1 26428.043381 # Average occupied blocks per context
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system.l2c.occ_percent::0 0.182600 # Average percentage of cache occupancy
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system.l2c.occ_percent::1 0.403260 # Average percentage of cache occupancy
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system.l2c.ReadReq_hits::0 2331798 # number of ReadReq hits
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system.l2c.ReadReq_hits::1 145238 # number of ReadReq hits
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system.l2c.ReadReq_hits::total 2477036 # number of ReadReq hits
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system.l2c.Writeback_hits::0 1588821 # number of Writeback hits
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system.l2c.Writeback_hits::total 1588821 # number of Writeback hits
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system.l2c.UpgradeReq_hits::0 321 # number of UpgradeReq hits
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system.l2c.UpgradeReq_hits::total 321 # number of UpgradeReq hits
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system.l2c.ReadExReq_hits::0 149873 # number of ReadExReq hits
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system.l2c.ReadExReq_hits::total 149873 # number of ReadExReq hits
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system.l2c.demand_hits::0 2481671 # number of demand (read+write) hits
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system.l2c.demand_hits::1 145238 # number of demand (read+write) hits
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system.l2c.demand_hits::total 2626909 # number of demand (read+write) hits
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system.l2c.overall_hits::0 2481671 # number of overall hits
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system.l2c.overall_hits::1 145238 # number of overall hits
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system.l2c.overall_hits::total 2626909 # number of overall hits
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system.l2c.ReadReq_misses::0 68032 # number of ReadReq misses
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system.l2c.ReadReq_misses::1 90 # number of ReadReq misses
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system.l2c.ReadReq_misses::total 68122 # number of ReadReq misses
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system.l2c.UpgradeReq_misses::0 3926 # number of UpgradeReq misses
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system.l2c.UpgradeReq_misses::total 3926 # number of UpgradeReq misses
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system.l2c.ReadExReq_misses::0 142738 # number of ReadExReq misses
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system.l2c.ReadExReq_misses::total 142738 # number of ReadExReq misses
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system.l2c.demand_misses::0 210770 # number of demand (read+write) misses
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system.l2c.demand_misses::1 90 # number of demand (read+write) misses
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system.l2c.demand_misses::total 210860 # number of demand (read+write) misses
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system.l2c.overall_misses::0 210770 # number of overall misses
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system.l2c.overall_misses::1 90 # number of overall misses
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system.l2c.overall_misses::total 210860 # number of overall misses
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system.l2c.ReadReq_miss_latency 3572833000 # number of ReadReq miss cycles
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system.l2c.UpgradeReq_miss_latency 39364500 # number of UpgradeReq miss cycles
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system.l2c.ReadExReq_miss_latency 7469371500 # number of ReadExReq miss cycles
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system.l2c.demand_miss_latency 11042204500 # number of demand (read+write) miss cycles
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system.l2c.overall_miss_latency 11042204500 # number of overall miss cycles
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system.l2c.ReadReq_accesses::0 2399830 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::1 145328 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::total 2545158 # number of ReadReq accesses(hits+misses)
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system.l2c.Writeback_accesses::0 1588821 # number of Writeback accesses(hits+misses)
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system.l2c.Writeback_accesses::total 1588821 # number of Writeback accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::0 4247 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::total 4247 # number of UpgradeReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::0 292611 # number of ReadExReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::total 292611 # number of ReadExReq accesses(hits+misses)
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system.l2c.demand_accesses::0 2692441 # number of demand (read+write) accesses
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system.l2c.demand_accesses::1 145328 # number of demand (read+write) accesses
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system.l2c.demand_accesses::total 2837769 # number of demand (read+write) accesses
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system.l2c.overall_accesses::0 2692441 # number of overall (read+write) accesses
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system.l2c.overall_accesses::1 145328 # number of overall (read+write) accesses
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system.l2c.overall_accesses::total 2837769 # number of overall (read+write) accesses
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system.l2c.ReadReq_miss_rate::0 0.028349 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::1 0.000619 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::total 0.028968 # miss rate for ReadReq accesses
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system.l2c.UpgradeReq_miss_rate::0 0.924417 # miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_miss_rate::0 0.487808 # miss rate for ReadExReq accesses
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system.l2c.demand_miss_rate::0 0.078282 # miss rate for demand accesses
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system.l2c.demand_miss_rate::1 0.000619 # miss rate for demand accesses
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system.l2c.demand_miss_rate::total 0.078901 # miss rate for demand accesses
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system.l2c.overall_miss_rate::0 0.078282 # miss rate for overall accesses
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system.l2c.overall_miss_rate::1 0.000619 # miss rate for overall accesses
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system.l2c.overall_miss_rate::total 0.078901 # miss rate for overall accesses
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system.l2c.ReadReq_avg_miss_latency::0 52516.947907 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::1 39698144.444444 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::total 39750661.392351 # average ReadReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::0 10026.617422 # average UpgradeReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::0 52329.243089 # average ReadExReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
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system.l2c.demand_avg_miss_latency::0 52389.830147 # average overall miss latency
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system.l2c.demand_avg_miss_latency::1 122691161.111111 # average overall miss latency
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system.l2c.demand_avg_miss_latency::total 122743550.941258 # average overall miss latency
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system.l2c.overall_avg_miss_latency::0 52389.830147 # average overall miss latency
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system.l2c.overall_avg_miss_latency::1 122691161.111111 # average overall miss latency
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system.l2c.overall_avg_miss_latency::total 122743550.941258 # average overall miss latency
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.l2c.fast_writes 0 # number of fast writes performed
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system.l2c.cache_copies 0 # number of cache copies performed
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system.l2c.writebacks 142383 # number of writebacks
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system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits
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system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits
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system.l2c.overall_mshr_hits 2 # number of overall MSHR hits
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system.l2c.ReadReq_mshr_misses 68120 # number of ReadReq MSHR misses
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system.l2c.UpgradeReq_mshr_misses 3926 # number of UpgradeReq MSHR misses
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system.l2c.ReadExReq_mshr_misses 142738 # number of ReadExReq MSHR misses
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system.l2c.demand_mshr_misses 210858 # number of demand (read+write) MSHR misses
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system.l2c.overall_mshr_misses 210858 # number of overall MSHR misses
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system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.l2c.ReadReq_mshr_miss_latency 2742078500 # number of ReadReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency 157403500 # number of UpgradeReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency 5729564000 # number of ReadExReq MSHR miss cycles
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system.l2c.demand_mshr_miss_latency 8471642500 # number of demand (read+write) MSHR miss cycles
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system.l2c.overall_mshr_miss_latency 8471642500 # number of overall MSHR miss cycles
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system.l2c.ReadReq_mshr_uncacheable_latency 61532429500 # number of ReadReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency 1222286000 # number of WriteReq MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency 62754715500 # number of overall MSHR uncacheable cycles
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system.l2c.ReadReq_mshr_miss_rate::0 0.028385 # mshr miss rate for ReadReq accesses
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system.l2c.ReadReq_mshr_miss_rate::1 0.468733 # mshr miss rate for ReadReq accesses
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system.l2c.ReadReq_mshr_miss_rate::total 0.497118 # mshr miss rate for ReadReq accesses
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system.l2c.UpgradeReq_mshr_miss_rate::0 0.924417 # mshr miss rate for UpgradeReq accesses
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system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
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system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::0 0.487808 # mshr miss rate for ReadExReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
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system.l2c.demand_mshr_miss_rate::0 0.078315 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::1 1.450911 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::total 1.529226 # mshr miss rate for demand accesses
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system.l2c.overall_mshr_miss_rate::0 0.078315 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::1 1.450911 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::total 1.529226 # mshr miss rate for overall accesses
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system.l2c.ReadReq_avg_mshr_miss_latency 40253.647974 # average ReadReq mshr miss latency
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system.l2c.UpgradeReq_avg_mshr_miss_latency 40092.587876 # average UpgradeReq mshr miss latency
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system.l2c.ReadExReq_avg_mshr_miss_latency 40140.425115 # average ReadExReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency 40177.003007 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency 40177.003007 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
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system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.iocache.replacements 47570 # number of replacements
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system.iocache.tagsinuse 0.129176 # Cycle average of tags in use
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system.iocache.total_refs 0 # Total number of references to valid blocks.
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system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
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system.iocache.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.warmup_cycle 4994509673000 # Cycle when the warmup percentage was hit.
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system.iocache.occ_blocks::1 0.129176 # Average occupied blocks per context
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system.iocache.occ_percent::1 0.008073 # Average percentage of cache occupancy
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system.iocache.demand_hits::0 0 # number of demand (read+write) hits
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system.iocache.demand_hits::1 0 # number of demand (read+write) hits
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system.iocache.demand_hits::total 0 # number of demand (read+write) hits
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system.iocache.overall_hits::0 0 # number of overall hits
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system.iocache.overall_hits::1 0 # number of overall hits
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system.iocache.overall_hits::total 0 # number of overall hits
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system.iocache.ReadReq_misses::1 905 # number of ReadReq misses
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system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
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system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses
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system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
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system.iocache.demand_misses::0 0 # number of demand (read+write) misses
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system.iocache.demand_misses::1 47625 # number of demand (read+write) misses
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system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
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system.iocache.overall_misses::0 0 # number of overall misses
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system.iocache.overall_misses::1 47625 # number of overall misses
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system.iocache.overall_misses::total 47625 # number of overall misses
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system.iocache.ReadReq_miss_latency 113496932 # number of ReadReq miss cycles
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system.iocache.WriteReq_miss_latency 6374731160 # number of WriteReq miss cycles
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system.iocache.demand_miss_latency 6488228092 # number of demand (read+write) miss cycles
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system.iocache.overall_miss_latency 6488228092 # number of overall miss cycles
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system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses)
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system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
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system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses)
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system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
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system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
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system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses
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system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
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system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
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system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses
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system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
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system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
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system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
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system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
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system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
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system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
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system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
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system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
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system.iocache.ReadReq_avg_miss_latency::1 125410.974586 # average ReadReq miss latency
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system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
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system.iocache.WriteReq_avg_miss_latency::1 136445.444349 # average WriteReq miss latency
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system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
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system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
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system.iocache.demand_avg_miss_latency::1 136235.760462 # average overall miss latency
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system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
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system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
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system.iocache.overall_avg_miss_latency::1 136235.760462 # average overall miss latency
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system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
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system.iocache.blocked_cycles::no_mshrs 68743556 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked::no_mshrs 11268 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_mshrs 6100.777068 # average number of cycles each access was blocked
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system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.iocache.fast_writes 0 # number of fast writes performed
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system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.writebacks 46667 # number of writebacks
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system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
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system.iocache.ReadReq_mshr_misses 905 # number of ReadReq MSHR misses
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system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses
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system.iocache.demand_mshr_misses 47625 # number of demand (read+write) MSHR misses
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system.iocache.overall_mshr_misses 47625 # number of overall MSHR misses
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system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.iocache.ReadReq_mshr_miss_latency 66413982 # number of ReadReq MSHR miss cycles
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system.iocache.WriteReq_mshr_miss_latency 3944974906 # number of WriteReq MSHR miss cycles
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system.iocache.demand_mshr_miss_latency 4011388888 # number of demand (read+write) MSHR miss cycles
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system.iocache.overall_mshr_miss_latency 4011388888 # number of overall MSHR miss cycles
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system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
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system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
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system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
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system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
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system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
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system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
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system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
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system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
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system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
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system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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system.iocache.ReadReq_avg_mshr_miss_latency 73385.615470 # average ReadReq mshr miss latency
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system.iocache.WriteReq_avg_mshr_miss_latency 84438.675214 # average WriteReq mshr miss latency
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system.iocache.demand_avg_mshr_miss_latency 84228.638068 # average overall mshr miss latency
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system.iocache.overall_avg_mshr_miss_latency 84228.638068 # average overall mshr miss latency
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system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
|
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
|
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
|
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
|
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.cpu.numCycles 449087853 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.BPredUnit.lookups 91217869 # Number of BP lookups
|
|
system.cpu.BPredUnit.condPredicted 91217869 # Number of conditional branches predicted
|
|
system.cpu.BPredUnit.condIncorrect 1248400 # Number of conditional branches incorrect
|
|
system.cpu.BPredUnit.BTBLookups 89951778 # Number of BTB lookups
|
|
system.cpu.BPredUnit.BTBHits 83914735 # Number of BTB hits
|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
|
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
|
system.cpu.fetch.icacheStallCycles 28382208 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 451447456 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 91217869 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 83914735 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 171329150 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 6161718 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 187674 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.BlockedCycles 82029365 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 36833 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 58090 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 9909586 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 559902 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 3975 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 286820350 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 3.091965 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.403436 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 116059602 40.46% 40.46% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 1498115 0.52% 40.99% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 72812872 25.39% 66.37% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 1272717 0.44% 66.82% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2053780 0.72% 67.53% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 3977163 1.39% 68.92% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 1588647 0.55% 69.47% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 2196057 0.77% 70.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 85361397 29.76% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 286820350 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.203118 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.005254 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 33356268 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 78574400 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 165851521 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 4241450 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 4796711 # Number of cycles decode is squashing
|
|
system.cpu.decode.DecodedInsts 882885518 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 603 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 4796711 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 37592669 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 52283630 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 10046208 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 165609505 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 16491627 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 878188662 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 14524 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 11489749 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 2124384 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 880584292 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 1724975571 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 1724975011 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 560 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 843343914 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 37240371 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 491374 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 493473 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 42595982 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 19743931 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 10730204 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1270430 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1078815 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 870972067 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 898477 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 866458351 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 218010 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 31071842 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 45598434 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 144784 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 286820350 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 3.020910 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.373009 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 82323990 28.70% 28.70% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 22353891 7.79% 36.50% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 14123864 4.92% 41.42% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 9769344 3.41% 44.83% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 79473928 27.71% 72.53% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 4992964 1.74% 74.28% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 72968378 25.44% 99.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 634028 0.22% 99.94% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 179963 0.06% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 286820350 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 195550 8.86% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 1820080 82.44% 91.30% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 192012 8.70% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 302678 0.03% 0.03% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 830926438 95.90% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 25678898 2.96% 98.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 9550337 1.10% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 866458351 # Type of FU issued
|
|
system.cpu.iq.rate 1.929374 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 2207642 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.002548 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 2022315315 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 902983728 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 855563326 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 258 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 55 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 868363218 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 1360799 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 4398376 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 17098 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 43182 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 2298641 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 7817204 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 161145 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 4796711 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 33445550 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 6029017 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 871870544 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 303715 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 19743931 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 10730246 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 897675 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 5516781 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 26023 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 43182 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 896575 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 530355 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1426930 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 864313806 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 25191099 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 2144544 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 34501157 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 86709322 # Number of branches executed
|
|
system.cpu.iew.exec_stores 9310058 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.924598 # Inst execution rate
|
|
system.cpu.iew.wb_sent 863645103 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 855563381 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 671472669 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1171866734 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.905114 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.572994 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitCommittedInsts 839951837 # The number of committed instructions
|
|
system.cpu.commit.commitSquashedInsts 31810372 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 753691 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1255440 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 282039656 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.978134 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.864065 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 102542445 36.36% 36.36% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 12533027 4.44% 40.80% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4681692 1.66% 42.46% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 76967359 27.29% 69.75% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 4010237 1.42% 71.17% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1852910 0.66% 71.83% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1082027 0.38% 72.21% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 71603983 25.39% 97.60% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 6765976 2.40% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 282039656 # Number of insts commited each cycle
|
|
system.cpu.commit.count 839951837 # Number of instructions committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 23777157 # Number of memory references committed
|
|
system.cpu.commit.loads 15345552 # Number of loads committed
|
|
system.cpu.commit.membars 801 # Number of memory barriers committed
|
|
system.cpu.commit.branches 85535847 # Number of branches committed
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 768568499 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 6765976 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 1146952939 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1748336346 # The number of ROB writes
|
|
system.cpu.timesIdled 3079654 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 162267503 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 839951837 # Number of Instructions Simulated
|
|
system.cpu.committedInsts_total 839951837 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.534659 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.534659 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.870351 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.870351 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 1407338355 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 857621513 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 55 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 282388563 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 410581 # number of misc regfile writes
|
|
system.cpu.icache.replacements 1030220 # number of replacements
|
|
system.cpu.icache.tagsinuse 510.462524 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 8809167 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 1030732 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 8.546515 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 54553868000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::0 510.462524 # Average occupied blocks per context
|
|
system.cpu.icache.occ_percent::0 0.996997 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::0 8809167 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 8809167 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::0 8809167 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 8809167 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::0 8809167 # number of overall hits
|
|
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 8809167 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::0 1100416 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1100416 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::0 1100416 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1100416 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::0 1100416 # number of overall misses
|
|
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1100416 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency 16477170489 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency 16477170489 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency 16477170489 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::0 9909583 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 9909583 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::0 9909583 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 9909583 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::0 9909583 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 9909583 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::0 0.111046 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::0 0.111046 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::0 0.111046 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::0 14973.583162 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::0 14973.583162 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::0 14973.583162 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 2487991 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 243 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 10238.646091 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks 1561 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits 67148 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits 67148 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits 67148 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses 1033268 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses 1033268 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses 1033268 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 12490519491 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency 12490519491 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency 12490519491 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.104270 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0.104270 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0.104270 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12088.363804 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 12088.363804 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 12088.363804 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.itb_walker_cache.replacements 13461 # number of replacements
|
|
system.cpu.itb_walker_cache.tagsinuse 5.999270 # Cycle average of tags in use
|
|
system.cpu.itb_walker_cache.total_refs 28519 # Total number of references to valid blocks.
|
|
system.cpu.itb_walker_cache.sampled_refs 13469 # Sample count of references to valid blocks.
|
|
system.cpu.itb_walker_cache.avg_refs 2.117381 # Average number of references to valid blocks.
|
|
system.cpu.itb_walker_cache.warmup_cycle 5126859452000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.itb_walker_cache.occ_blocks::1 5.999270 # Average occupied blocks per context
|
|
system.cpu.itb_walker_cache.occ_percent::1 0.374954 # Average percentage of cache occupancy
|
|
system.cpu.itb_walker_cache.ReadReq_hits::1 28575 # number of ReadReq hits
|
|
system.cpu.itb_walker_cache.ReadReq_hits::total 28575 # number of ReadReq hits
|
|
system.cpu.itb_walker_cache.WriteReq_hits::1 3 # number of WriteReq hits
|
|
system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits
|
|
system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.demand_hits::1 28578 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.demand_hits::total 28578 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits
|
|
system.cpu.itb_walker_cache.overall_hits::1 28578 # number of overall hits
|
|
system.cpu.itb_walker_cache.overall_hits::total 28578 # number of overall hits
|
|
system.cpu.itb_walker_cache.ReadReq_misses::1 14318 # number of ReadReq misses
|
|
system.cpu.itb_walker_cache.ReadReq_misses::total 14318 # number of ReadReq misses
|
|
system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.demand_misses::1 14318 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.demand_misses::total 14318 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses
|
|
system.cpu.itb_walker_cache.overall_misses::1 14318 # number of overall misses
|
|
system.cpu.itb_walker_cache.overall_misses::total 14318 # number of overall misses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency 183495000 # number of ReadReq miss cycles
|
|
system.cpu.itb_walker_cache.demand_miss_latency 183495000 # number of demand (read+write) miss cycles
|
|
system.cpu.itb_walker_cache.overall_miss_latency 183495000 # number of overall miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::1 42893 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::total 42893 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.demand_accesses::1 42896 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.demand_accesses::total 42896 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::1 42896 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::total 42896 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.333807 # miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::1 0.333784 # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::1 0.333784 # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12815.686548 # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12815.686548 # average overall miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12815.686548 # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.itb_walker_cache.writebacks 2322 # number of writebacks
|
|
system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses 14318 # number of ReadReq MSHR misses
|
|
system.cpu.itb_walker_cache.demand_mshr_misses 14318 # number of demand (read+write) MSHR misses
|
|
system.cpu.itb_walker_cache.overall_mshr_misses 14318 # number of overall MSHR misses
|
|
system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 140154000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency 140154000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency 140154000 # number of overall MSHR miss cycles
|
|
system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.333807 # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.333784 # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.333784 # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9788.657634 # average ReadReq mshr miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9788.657634 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9788.657634 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dtb_walker_cache.replacements 143345 # number of replacements
|
|
system.cpu.dtb_walker_cache.tagsinuse 13.852844 # Cycle average of tags in use
|
|
system.cpu.dtb_walker_cache.total_refs 148404 # Total number of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.sampled_refs 143358 # Sample count of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.avg_refs 1.035199 # Average number of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.warmup_cycle 5098934943000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dtb_walker_cache.occ_blocks::1 13.852844 # Average occupied blocks per context
|
|
system.cpu.dtb_walker_cache.occ_percent::1 0.865803 # Average percentage of cache occupancy
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::1 148429 # number of ReadReq hits
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 148429 # number of ReadReq hits
|
|
system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.demand_hits::1 148429 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.demand_hits::total 148429 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits
|
|
system.cpu.dtb_walker_cache.overall_hits::1 148429 # number of overall hits
|
|
system.cpu.dtb_walker_cache.overall_hits::total 148429 # number of overall hits
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::1 144294 # number of ReadReq misses
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 144294 # number of ReadReq misses
|
|
system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.demand_misses::1 144294 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.demand_misses::total 144294 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses
|
|
system.cpu.dtb_walker_cache.overall_misses::1 144294 # number of overall misses
|
|
system.cpu.dtb_walker_cache.overall_misses::total 144294 # number of overall misses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency 1999592000 # number of ReadReq miss cycles
|
|
system.cpu.dtb_walker_cache.demand_miss_latency 1999592000 # number of demand (read+write) miss cycles
|
|
system.cpu.dtb_walker_cache.overall_miss_latency 1999592000 # number of overall miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::1 292723 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 292723 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.demand_accesses::1 292723 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 292723 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::1 292723 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 292723 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.492937 # miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::1 0.492937 # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::1 0.492937 # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13857.762624 # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13857.762624 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13857.762624 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dtb_walker_cache.writebacks 36787 # number of writebacks
|
|
system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses 144294 # number of ReadReq MSHR misses
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses 144294 # number of demand (read+write) MSHR misses
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses 144294 # number of overall MSHR misses
|
|
system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1562734500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1562734500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1562734500 # number of overall MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.492937 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.492937 # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.492937 # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10830.211235 # average ReadReq mshr miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10830.211235 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10830.211235 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1661784 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.998465 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 18023326 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1662296 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 10.842429 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 13135000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::0 511.998465 # Average occupied blocks per context
|
|
system.cpu.dcache.occ_percent::0 0.999997 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::0 11452816 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 11452816 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::0 6548488 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 6548488 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::0 18001304 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 18001304 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::0 18001304 # number of overall hits
|
|
system.cpu.dcache.overall_hits::1 0 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 18001304 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::0 2480783 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 2480783 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::0 1873809 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1873809 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::0 4354592 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 4354592 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::0 4354592 # number of overall misses
|
|
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 4354592 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency 37442770000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency 63502469838 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency 100945239838 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency 100945239838 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::0 13933599 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 13933599 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::0 8422297 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 8422297 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::0 22355896 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 22355896 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::0 22355896 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 22355896 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::0 0.178043 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::0 0.222482 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::0 0.194785 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::0 0.194785 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::0 15093.125840 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::0 33889.510531 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::0 23181.331302 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::0 23181.331302 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 1084772653 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 6673000 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 73247 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 392 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14809.789520 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 17022.959184 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks 1548151 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits 1110544 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits 1577040 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits 2687584 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits 2687584 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses 1370239 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses 296769 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses 1667008 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses 1667008 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 18185435000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 9767723153 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency 27953158153 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency 27953158153 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86946921000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1385819000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 88332740000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098341 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035236 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::0 0.074567 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::0 0.074567 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13271.724860 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32913.556177 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 16768.460711 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 16768.460711 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|