81d5ffe7de
some sundry problems with new interface
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Fixed to use new FunctionalMemory interface
--HG--
extra : convert_revision : bee98e6285d92f28fafacf919ab06eaf333a9b56
92 lines
3 KiB
C++
92 lines
3 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Emulation of the Tsunami CChip CSRs
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*/
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#ifndef __TSUNAMI_CCHIP_HH__
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#define __TSUNAMI_CCHIP_HH__
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#include "mem/functional_mem/functional_memory.hh"
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#include "dev/tsunami.hh"
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/*
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* Tsunami CChip
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*/
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class TsunamiCChip : public FunctionalMemory
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{
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private:
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Addr addr;
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static const Addr size = 0xfff;
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protected:
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/**
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* pointer to the tsunami object.
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* This is our access to all the other tsunami
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* devices.
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*/
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Tsunami *tsunami;
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/**
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* The dims are device interrupt mask registers.
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* One exists for each CPU, the DRIR X DIM = DIR
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*/
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uint64_t dim[Tsunami::Max_CPUs];
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/**
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* The dirs are device interrupt registers.
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* One exists for each CPU, the DRIR X DIM = DIR
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*/
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uint64_t dir[Tsunami::Max_CPUs];
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bool dirInterrupting[Tsunami::Max_CPUs];
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/**
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* This register contains bits for each PCI interrupt
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* that can occur.
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*/
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uint64_t drir;
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public:
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TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
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MemoryController *mmu);
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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void postDRIR(uint64_t bitvector);
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void clearDRIR(uint64_t bitvector);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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uint64_t misc;
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bool RTCInterrupting;
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};
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#endif // __TSUNAMI_CCHIP_HH__
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