25e1b1c1f5
This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
1645 lines
187 KiB
Plaintext
1645 lines
187 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000260 # Number of seconds simulated
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sim_ticks 260073500 # Number of ticks simulated
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final_tick 260073500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1077387 # Simulator instruction rate (inst/s)
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host_op_rate 1077364 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 425087977 # Simulator tick rate (ticks/s)
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host_mem_usage 303432 # Number of bytes of host memory used
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host_seconds 0.61 # Real time elapsed on the host
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sim_insts 659129 # Number of instructions simulated
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sim_ops 659129 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1024 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 3456 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 16 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 70134020 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 40603906 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 3445180 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 3937348 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 13288551 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 5413854 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.inst 246084 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.data 3691264 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 140760208 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 70134020 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 3445180 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 13288551 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu3.inst 246084 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 87113835 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 70134020 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 40603906 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 3445180 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 3937348 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 13288551 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 5413854 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.inst 246084 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.data 3691264 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 140760208 # Total bandwidth to/from this memory (bytes/s)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu0.workload.num_syscalls 89 # Number of system calls
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system.cpu0.numCycles 520147 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.committedInsts 157434 # Number of instructions committed
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system.cpu0.committedOps 157434 # Number of ops (including micro ops) committed
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system.cpu0.num_int_alu_accesses 108448 # Number of integer alu accesses
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system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu0.num_func_calls 390 # number of times a function call or return occured
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system.cpu0.num_conditional_control_insts 25842 # number of instructions that are conditional controls
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system.cpu0.num_int_insts 108448 # number of integer instructions
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system.cpu0.num_fp_insts 0 # number of float instructions
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system.cpu0.num_int_register_reads 313502 # number of times the integer registers were read
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system.cpu0.num_int_register_writes 110054 # number of times the integer registers were written
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system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu0.num_mem_refs 73451 # number of memory refs
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system.cpu0.num_load_insts 48627 # Number of load instructions
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system.cpu0.num_store_insts 24824 # Number of store instructions
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system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
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system.cpu0.num_busy_cycles 520146.998000 # Number of busy cycles
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system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
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system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
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system.cpu0.Branches 26707 # Number of branches fetched
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system.cpu0.op_class::No_OpClass 23434 14.88% 14.88% # Class of executed instruction
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system.cpu0.op_class::IntAlu 60527 38.43% 53.31% # Class of executed instruction
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system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::FloatCmp 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::FloatCvt 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::FloatMult 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::FloatDiv 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::FloatSqrt 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdAdd 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdAddAcc 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdAlu 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdCmp 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdCvt 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdMisc 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdMult 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdMultAcc 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdShift 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdSqrt 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction
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system.cpu0.op_class::MemRead 48711 30.93% 84.24% # Class of executed instruction
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system.cpu0.op_class::MemWrite 24824 15.76% 100.00% # Class of executed instruction
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu0.op_class::total 157496 # Class of executed instruction
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system.cpu0.dcache.tags.replacements 2 # number of replacements
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system.cpu0.dcache.tags.tagsinuse 145.650768 # Cycle average of tags in use
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system.cpu0.dcache.tags.total_refs 72919 # Total number of references to valid blocks.
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system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
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system.cpu0.dcache.tags.avg_refs 436.640719 # Average number of references to valid blocks.
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system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.650768 # Average occupied blocks per requestor
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system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284474 # Average percentage of cache occupancy
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system.cpu0.dcache.tags.occ_percent::total 0.284474 # Average percentage of cache occupancy
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
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system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
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system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
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system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
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system.cpu0.dcache.tags.tag_accesses 294037 # Number of tag accesses
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system.cpu0.dcache.tags.data_accesses 294037 # Number of data accesses
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system.cpu0.dcache.ReadReq_hits::cpu0.data 48447 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_hits::total 48447 # number of ReadReq hits
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system.cpu0.dcache.WriteReq_hits::cpu0.data 24590 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::total 24590 # number of WriteReq hits
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system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
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system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
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system.cpu0.dcache.demand_hits::cpu0.data 73037 # number of demand (read+write) hits
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system.cpu0.dcache.demand_hits::total 73037 # number of demand (read+write) hits
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system.cpu0.dcache.overall_hits::cpu0.data 73037 # number of overall hits
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system.cpu0.dcache.overall_hits::total 73037 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses
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system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
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system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
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system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
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system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses
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system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses
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system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses
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system.cpu0.dcache.overall_misses::total 353 # number of overall misses
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system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4613500 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_latency::total 4613500 # number of ReadReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976500 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::total 6976500 # number of WriteReq miss cycles
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system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles
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system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles
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system.cpu0.dcache.demand_miss_latency::cpu0.data 11590000 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_latency::total 11590000 # number of demand (read+write) miss cycles
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system.cpu0.dcache.overall_miss_latency::cpu0.data 11590000 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_latency::total 11590000 # number of overall miss cycles
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system.cpu0.dcache.ReadReq_accesses::cpu0.data 48617 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_accesses::total 48617 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::cpu0.data 24773 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::total 24773 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
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system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
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system.cpu0.dcache.demand_accesses::cpu0.data 73390 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_accesses::total 73390 # number of demand (read+write) accesses
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system.cpu0.dcache.overall_accesses::cpu0.data 73390 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_accesses::total 73390 # number of overall (read+write) accesses
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system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003497 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_miss_rate::total 0.003497 # miss rate for ReadReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007387 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::total 0.007387 # miss rate for WriteReq accesses
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system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
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system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
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system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004810 # miss rate for demand accesses
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system.cpu0.dcache.demand_miss_rate::total 0.004810 # miss rate for demand accesses
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system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004810 # miss rate for overall accesses
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system.cpu0.dcache.overall_miss_rate::total 0.004810 # miss rate for overall accesses
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system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27138.235294 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_miss_latency::total 27138.235294 # average ReadReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38122.950820 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::total 38122.950820 # average WriteReq miss latency
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system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency
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system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency
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system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency
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system.cpu0.dcache.demand_avg_miss_latency::total 32832.861190 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::total 32832.861190 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
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system.cpu0.dcache.writebacks::total 1 # number of writebacks
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system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses
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system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses
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|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
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|
system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
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|
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
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|
system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4443500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4443500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6793500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6793500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 333000 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 333000 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11237000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 11237000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11237000 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency::total 11237000 # number of overall MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003497 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003497 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007387 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007387 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.004810 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.004810 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26138.235294 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26138.235294 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37122.950820 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37122.950820 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12807.692308 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 215 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 212.583222 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 157030 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 336.252677 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.583222 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415202 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.415202 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 157964 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 157964 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 157030 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 157030 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 157030 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 157030 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 157030 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 157030 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 467 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18042500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 18042500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 18042500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 18042500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 18042500 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 18042500 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 157497 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 157497 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 157497 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 157497 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 157497 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 157497 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002965 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.002965 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002965 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.002965 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002965 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.002965 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38634.903640 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 38634.903640 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 38634.903640 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 38634.903640 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17575500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 17575500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17575500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 17575500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17575500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 17575500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002965 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.002965 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.002965 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37634.903640 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.numCycles 520147 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 165571 # Number of instructions committed
|
|
system.cpu1.committedOps 165571 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 111555 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 637 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 31016 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 111555 # number of integer instructions
|
|
system.cpu1.num_fp_insts 0 # number of float instructions
|
|
system.cpu1.num_int_register_reads 284333 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 108565 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 56707 # number of memory refs
|
|
system.cpu1.num_load_insts 41448 # Number of load instructions
|
|
system.cpu1.num_store_insts 15259 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 452419.998260 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.869793 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.130207 # Percentage of idle cycles
|
|
system.cpu1.Branches 32668 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 23452 14.16% 14.16% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 74986 45.28% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.44% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 51906 31.34% 90.79% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 15259 9.21% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 165603 # Class of executed instruction
|
|
system.cpu1.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 26.035238 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 32753 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 1129.413793 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.035238 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050850 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.050850 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 227042 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 227042 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 41284 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 41284 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 15082 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 15082 # number of WriteReq hits
|
|
system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits
|
|
system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 56366 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 56366 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 56366 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 56366 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 156 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 156 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses
|
|
system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses
|
|
system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 265 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 265 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 265 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 265 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2383000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 2383000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2068000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 2068000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 251500 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::total 251500 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 4451000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 4451000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 4451000 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 4451000 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 41440 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 41440 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 15191 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 15191 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 56631 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 56631 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 56631 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 56631 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003764 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007175 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.007175 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.833333 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004679 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.004679 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004679 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.004679 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15275.641026 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15275.641026 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18972.477064 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18972.477064 # average WriteReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4572.727273 # average SwapReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::total 4572.727273 # average SwapReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 16796.226415 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 16796.226415 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2227000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2227000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1959000 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1959000 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 196500 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 196500 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4186000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 4186000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4186000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 4186000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003764 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007175 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007175 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.833333 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.004679 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.004679 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14275.641026 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14275.641026 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17972.477064 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17972.477064 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3572.727273 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3572.727273 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 280 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 65.699918 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 165238 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 451.469945 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.699918 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128320 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.128320 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 165970 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 165970 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 165238 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 165238 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 165238 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 165238 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 165238 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 165238 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 366 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5351500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 5351500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 5351500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 5351500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 5351500 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 5351500 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 165604 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 165604 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 165604 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 165604 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 165604 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 165604 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002210 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002210 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002210 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14621.584699 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 14621.584699 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 14621.584699 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 14621.584699 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4985500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4985500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4985500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 4985500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4985500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 4985500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13621.584699 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.numCycles 520146 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.committedInsts 160598 # Number of instructions committed
|
|
system.cpu2.committedOps 160598 # Number of ops (including micro ops) committed
|
|
system.cpu2.num_int_alu_accesses 111601 # Number of integer alu accesses
|
|
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu2.num_func_calls 637 # number of times a function call or return occured
|
|
system.cpu2.num_conditional_control_insts 28506 # number of instructions that are conditional controls
|
|
system.cpu2.num_int_insts 111601 # number of integer instructions
|
|
system.cpu2.num_fp_insts 0 # number of float instructions
|
|
system.cpu2.num_int_register_reads 294560 # number of times the integer registers were read
|
|
system.cpu2.num_int_register_writes 113655 # number of times the integer registers were written
|
|
system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu2.num_mem_refs 59264 # number of memory refs
|
|
system.cpu2.num_load_insts 41473 # Number of load instructions
|
|
system.cpu2.num_store_insts 17791 # Number of store instructions
|
|
system.cpu2.num_idle_cycles 67981.871041 # Number of idle cycles
|
|
system.cpu2.num_busy_cycles 452164.128959 # Number of busy cycles
|
|
system.cpu2.not_idle_fraction 0.869302 # Percentage of non-idle cycles
|
|
system.cpu2.idle_fraction 0.130698 # Percentage of idle cycles
|
|
system.cpu2.Branches 30158 # Number of branches fetched
|
|
system.cpu2.op_class::No_OpClass 20943 13.04% 13.04% # Class of executed instruction
|
|
system.cpu2.op_class::IntAlu 75009 46.70% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::IntMult 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::IntDiv 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::FloatAdd 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::FloatCmp 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::FloatCvt 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::FloatMult 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::FloatDiv 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::FloatSqrt 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdAdd 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdAddAcc 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdAlu 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdCmp 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdCvt 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdMisc 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdMult 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdMultAcc 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdShift 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdSqrt 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatMult 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.73% # Class of executed instruction
|
|
system.cpu2.op_class::MemRead 46887 29.19% 88.92% # Class of executed instruction
|
|
system.cpu2.op_class::MemWrite 17791 11.08% 100.00% # Class of executed instruction
|
|
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu2.op_class::total 160630 # Class of executed instruction
|
|
system.cpu2.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu2.dcache.tags.tagsinuse 27.808310 # Cycle average of tags in use
|
|
system.cpu2.dcache.tags.total_refs 37821 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.tags.avg_refs 1304.172414 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.808310 # Average occupied blocks per requestor
|
|
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054313 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_percent::total 0.054313 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
|
|
system.cpu2.dcache.tags.tag_accesses 237265 # Number of tag accesses
|
|
system.cpu2.dcache.tags.data_accesses 237265 # Number of data accesses
|
|
system.cpu2.dcache.ReadReq_hits::cpu2.data 41314 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_hits::total 41314 # number of ReadReq hits
|
|
system.cpu2.dcache.WriteReq_hits::cpu2.data 17614 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_hits::total 17614 # number of WriteReq hits
|
|
system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits
|
|
system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits
|
|
system.cpu2.dcache.demand_hits::cpu2.data 58928 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_hits::total 58928 # number of demand (read+write) hits
|
|
system.cpu2.dcache.overall_hits::cpu2.data 58928 # number of overall hits
|
|
system.cpu2.dcache.overall_hits::total 58928 # number of overall hits
|
|
system.cpu2.dcache.ReadReq_misses::cpu2.data 151 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_misses::total 151 # number of ReadReq misses
|
|
system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses
|
|
system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses
|
|
system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
|
|
system.cpu2.dcache.demand_misses::cpu2.data 261 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_misses::total 261 # number of demand (read+write) misses
|
|
system.cpu2.dcache.overall_misses::cpu2.data 261 # number of overall misses
|
|
system.cpu2.dcache.overall_misses::total 261 # number of overall misses
|
|
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2416500 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_latency::total 2416500 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2235500 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::total 2235500 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 248000 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::total 248000 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::cpu2.data 4652000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::total 4652000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::cpu2.data 4652000 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::total 4652000 # number of overall miss cycles
|
|
system.cpu2.dcache.ReadReq_accesses::cpu2.data 41465 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_accesses::total 41465 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::cpu2.data 17724 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::total 17724 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::cpu2.data 65 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.demand_accesses::cpu2.data 59189 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_accesses::total 59189 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::cpu2.data 59189 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::total 59189 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003642 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::total 0.003642 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006206 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::total 0.006206 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.846154 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::total 0.846154 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004410 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_miss_rate::total 0.004410 # miss rate for demand accesses
|
|
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004410 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_miss_rate::total 0.004410 # miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.311258 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::total 16003.311258 # average ReadReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20322.727273 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::total 20322.727273 # average WriteReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4509.090909 # average SwapReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::total 4509.090909 # average SwapReq miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::total 17823.754789 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::total 17823.754789 # average overall miss latency
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 151 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::cpu2.data 261 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::cpu2.data 261 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2265500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2265500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2125500 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2125500 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193000 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193000 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4391000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::total 4391000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4391000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::total 4391000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003642 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003642 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006206 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006206 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.846154 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::total 0.004410 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::total 0.004410 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15003.311258 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15003.311258 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19322.727273 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19322.727273 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3509.090909 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3509.090909 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.icache.tags.replacements 280 # number of replacements
|
|
system.cpu2.icache.tags.tagsinuse 70.147178 # Cycle average of tags in use
|
|
system.cpu2.icache.tags.total_refs 160265 # Total number of references to valid blocks.
|
|
system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.tags.avg_refs 437.882514 # Average number of references to valid blocks.
|
|
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.147178 # Average occupied blocks per requestor
|
|
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137006 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_percent::total 0.137006 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
|
|
system.cpu2.icache.tags.tag_accesses 160997 # Number of tag accesses
|
|
system.cpu2.icache.tags.data_accesses 160997 # Number of data accesses
|
|
system.cpu2.icache.ReadReq_hits::cpu2.inst 160265 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_hits::total 160265 # number of ReadReq hits
|
|
system.cpu2.icache.demand_hits::cpu2.inst 160265 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_hits::total 160265 # number of demand (read+write) hits
|
|
system.cpu2.icache.overall_hits::cpu2.inst 160265 # number of overall hits
|
|
system.cpu2.icache.overall_hits::total 160265 # number of overall hits
|
|
system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses
|
|
system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
|
|
system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
|
|
system.cpu2.icache.overall_misses::total 366 # number of overall misses
|
|
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7437500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_latency::total 7437500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.demand_miss_latency::cpu2.inst 7437500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_latency::total 7437500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.overall_miss_latency::cpu2.inst 7437500 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_latency::total 7437500 # number of overall miss cycles
|
|
system.cpu2.icache.ReadReq_accesses::cpu2.inst 160631 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_accesses::total 160631 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.demand_accesses::cpu2.inst 160631 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_accesses::total 160631 # number of demand (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::cpu2.inst 160631 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::total 160631 # number of overall (read+write) accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002279 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::total 0.002279 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002279 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_miss_rate::total 0.002279 # miss rate for demand accesses
|
|
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002279 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_miss_rate::total 0.002279 # miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20321.038251 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::total 20321.038251 # average ReadReq miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::total 20321.038251 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::total 20321.038251 # average overall miss latency
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7071500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::total 7071500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7071500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::total 7071500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7071500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::total 7071500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002279 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::total 0.002279 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::total 0.002279 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19321.038251 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.numCycles 520146 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.committedInsts 175526 # Number of instructions committed
|
|
system.cpu3.committedOps 175526 # Number of ops (including micro ops) committed
|
|
system.cpu3.num_int_alu_accesses 107877 # Number of integer alu accesses
|
|
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu3.num_func_calls 637 # number of times a function call or return occured
|
|
system.cpu3.num_conditional_control_insts 37833 # number of instructions that are conditional controls
|
|
system.cpu3.num_int_insts 107877 # number of integer instructions
|
|
system.cpu3.num_fp_insts 0 # number of float instructions
|
|
system.cpu3.num_int_register_reads 242346 # number of times the integer registers were read
|
|
system.cpu3.num_int_register_writes 89400 # number of times the integer registers were written
|
|
system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu3.num_mem_refs 46213 # number of memory refs
|
|
system.cpu3.num_load_insts 39592 # Number of load instructions
|
|
system.cpu3.num_store_insts 6621 # Number of store instructions
|
|
system.cpu3.num_idle_cycles 68237.870548 # Number of idle cycles
|
|
system.cpu3.num_busy_cycles 451908.129452 # Number of busy cycles
|
|
system.cpu3.not_idle_fraction 0.868810 # Percentage of non-idle cycles
|
|
system.cpu3.idle_fraction 0.131190 # Percentage of idle cycles
|
|
system.cpu3.Branches 39491 # Number of branches fetched
|
|
system.cpu3.op_class::No_OpClass 30262 17.24% 17.24% # Class of executed instruction
|
|
system.cpu3.op_class::IntAlu 73148 41.67% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::IntMult 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::IntDiv 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::FloatAdd 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::FloatCmp 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::FloatCvt 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::FloatMult 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::FloatDiv 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::FloatSqrt 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdAdd 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdAddAcc 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdAlu 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdCmp 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdCvt 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdMisc 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdMult 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdMultAcc 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdShift 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdSqrt 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatMult 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.90% # Class of executed instruction
|
|
system.cpu3.op_class::MemRead 65527 37.32% 96.23% # Class of executed instruction
|
|
system.cpu3.op_class::MemWrite 6621 3.77% 100.00% # Class of executed instruction
|
|
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu3.op_class::total 175558 # Class of executed instruction
|
|
system.cpu3.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu3.dcache.tags.tagsinuse 26.732151 # Cycle average of tags in use
|
|
system.cpu3.dcache.tags.total_refs 15554 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.tags.avg_refs 518.466667 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.732151 # Average occupied blocks per requestor
|
|
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052211 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_percent::total 0.052211 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
|
|
system.cpu3.dcache.tags.tag_accesses 185088 # Number of tag accesses
|
|
system.cpu3.dcache.tags.data_accesses 185088 # Number of data accesses
|
|
system.cpu3.dcache.ReadReq_hits::cpu3.data 39402 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_hits::total 39402 # number of ReadReq hits
|
|
system.cpu3.dcache.WriteReq_hits::cpu3.data 6435 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_hits::total 6435 # number of WriteReq hits
|
|
system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits
|
|
system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits
|
|
system.cpu3.dcache.demand_hits::cpu3.data 45837 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_hits::total 45837 # number of demand (read+write) hits
|
|
system.cpu3.dcache.overall_hits::cpu3.data 45837 # number of overall hits
|
|
system.cpu3.dcache.overall_hits::total 45837 # number of overall hits
|
|
system.cpu3.dcache.ReadReq_misses::cpu3.data 182 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_misses::total 182 # number of ReadReq misses
|
|
system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses
|
|
system.cpu3.dcache.SwapReq_misses::cpu3.data 60 # number of SwapReq misses
|
|
system.cpu3.dcache.SwapReq_misses::total 60 # number of SwapReq misses
|
|
system.cpu3.dcache.demand_misses::cpu3.data 287 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_misses::total 287 # number of demand (read+write) misses
|
|
system.cpu3.dcache.overall_misses::cpu3.data 287 # number of overall misses
|
|
system.cpu3.dcache.overall_misses::total 287 # number of overall misses
|
|
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3223000 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_latency::total 3223000 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1728500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::total 1728500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 276500 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::total 276500 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::cpu3.data 4951500 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::total 4951500 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::cpu3.data 4951500 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::total 4951500 # number of overall miss cycles
|
|
system.cpu3.dcache.ReadReq_accesses::cpu3.data 39584 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_accesses::total 39584 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::cpu3.data 6540 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::total 6540 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::cpu3.data 79 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.demand_accesses::cpu3.data 46124 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_accesses::total 46124 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::cpu3.data 46124 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::total 46124 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004598 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::total 0.004598 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016055 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::total 0.016055 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.759494 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::total 0.759494 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006222 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_miss_rate::total 0.006222 # miss rate for demand accesses
|
|
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006222 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_miss_rate::total 0.006222 # miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17708.791209 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::total 17708.791209 # average ReadReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16461.904762 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::total 16461.904762 # average WriteReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4608.333333 # average SwapReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::total 4608.333333 # average SwapReq miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::total 17252.613240 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::total 17252.613240 # average overall miss latency
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 182 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 60 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::cpu3.data 287 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::cpu3.data 287 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3041000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3041000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1623500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1623500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 216500 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 216500 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4664500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::total 4664500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4664500 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::total 4664500 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004598 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004598 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016055 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016055 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.759494 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.759494 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::total 0.006222 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::total 0.006222 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16708.791209 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16708.791209 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15461.904762 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15461.904762 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3608.333333 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3608.333333 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.icache.tags.replacements 281 # number of replacements
|
|
system.cpu3.icache.tags.tagsinuse 67.821849 # Cycle average of tags in use
|
|
system.cpu3.icache.tags.total_refs 175192 # Total number of references to valid blocks.
|
|
system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.tags.avg_refs 477.362398 # Average number of references to valid blocks.
|
|
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.821849 # Average occupied blocks per requestor
|
|
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132465 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_percent::total 0.132465 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
|
|
system.cpu3.icache.tags.tag_accesses 175926 # Number of tag accesses
|
|
system.cpu3.icache.tags.data_accesses 175926 # Number of data accesses
|
|
system.cpu3.icache.ReadReq_hits::cpu3.inst 175192 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_hits::total 175192 # number of ReadReq hits
|
|
system.cpu3.icache.demand_hits::cpu3.inst 175192 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_hits::total 175192 # number of demand (read+write) hits
|
|
system.cpu3.icache.overall_hits::cpu3.inst 175192 # number of overall hits
|
|
system.cpu3.icache.overall_hits::total 175192 # number of overall hits
|
|
system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses
|
|
system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses
|
|
system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses
|
|
system.cpu3.icache.overall_misses::total 367 # number of overall misses
|
|
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5136500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_latency::total 5136500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.demand_miss_latency::cpu3.inst 5136500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_latency::total 5136500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.overall_miss_latency::cpu3.inst 5136500 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_latency::total 5136500 # number of overall miss cycles
|
|
system.cpu3.icache.ReadReq_accesses::cpu3.inst 175559 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_accesses::total 175559 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.demand_accesses::cpu3.inst 175559 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_accesses::total 175559 # number of demand (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::cpu3.inst 175559 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::total 175559 # number of overall (read+write) accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002090 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::total 0.002090 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002090 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_miss_rate::total 0.002090 # miss rate for demand accesses
|
|
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002090 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_miss_rate::total 0.002090 # miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13995.912807 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::total 13995.912807 # average ReadReq miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::total 13995.912807 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::total 13995.912807 # average overall miss latency
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4769500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::total 4769500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4769500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::total 4769500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4769500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::total 4769500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002090 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::total 0.002090 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::total 0.002090 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12995.912807 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::total 12995.912807 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12995.912807 # average overall mshr miss latency
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 0 # number of replacements
|
|
system.l2c.tags.tagsinuse 349.351676 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 1716 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 4 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 0.890425 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 231.950289 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 54.237156 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 6.367865 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 0.832949 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 47.203910 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 6.135421 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.inst 0.888032 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.data 0.845628 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.003539 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.000097 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.000720 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.005331 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 19677 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 19677 # Number of data accesses
|
|
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 1 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu2.inst 302 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 302 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 352 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 302 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 3 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
|
|
system.l2c.overall_hits::total 1220 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu3.data 11 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu2.inst 64 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu3.inst 9 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 372 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 64 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 592 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 165 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 14 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 16 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 64 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 23 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 16 # number of overall misses
|
|
system.l2c.overall_misses::total 592 # number of overall misses
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 5197500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 735000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 797000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3.data 744000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 7473500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 14964000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 740000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3341500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu3.inst 453500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 19499000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 3465000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 105000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu2.data 419000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu3.data 104500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 4093500 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 14964000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 8662500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 740000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 840000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 3341500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 1216000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.inst 453500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.data 848500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 31066000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 14964000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 8662500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 740000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 840000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 3341500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 1216000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.inst 453500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.data 848500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 31066000 # number of overall miss cycles
|
|
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu3.data 11 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu3.inst 367 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 1566 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 11 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu2.data 11 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu3.data 11 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 104 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.237548 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.750000 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.174863 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.174863 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52500 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53133.333333 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 53142.857143 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 52630.281690 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52505.263158 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 52857.142857 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 52210.937500 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 50388.888889 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 52416.666667 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 52500 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 52500 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 52375 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 52250 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 52480.769231 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 52505.263158 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 52500 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 52857.142857 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 52500 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 52210.937500 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 52869.565217 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.inst 50388.888889 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.data 53031.250000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 52476.351351 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 52505.263158 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 52500 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 52857.142857 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 52500 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 52210.937500 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 52869.565217 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.inst 50388.888889 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.data 53031.250000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 52476.351351 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 10 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 8 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu2.data 1 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu3.data 1 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.inst 8 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu3.data 11 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 285 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 14 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 54 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 1 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 354 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 66 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 7 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 76 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 16 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 54 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 22 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 16 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 54 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 22 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1194000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 765000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 850000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 479492 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 3288492 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4207500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 595000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 647000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 604000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 6053500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 12114000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 600000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2295500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 42500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 15052000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 2805000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 85000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 297500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 42500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 3230000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 12114000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 7012500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 600000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 680000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 2295500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 944500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.inst 42500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.data 646500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 24335500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 12114000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 7012500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 600000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 680000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 2295500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 944500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.inst 42500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.data 646500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 24335500 # number of overall MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.181818 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.636364 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.640000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.640000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 42642.857143 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 42500 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 42500 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43590.181818 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42707.688312 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43133.333333 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 43142.857143 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 42630.281690 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 42500 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42519.774011 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 42500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 42500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadResp 430 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 272 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 77 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 208 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 142 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 261 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 914 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 914 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 914 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 665648 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2948008 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
|
|
system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 846 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 383 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 5316 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 1037 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 3986 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::7 3986 100.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 3986 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 1998491 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 503490 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 549000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 419983 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer4.occupancy 553988 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer5.occupancy 412483 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer6.occupancy 554487 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer7.occupancy 467954 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
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