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gem5/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
Andreas Hansson 25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes 
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.117365 # Number of seconds simulated
sim_ticks 1117365374500 # Number of ticks simulated
final_tick 1117365374500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 236504 # Simulator instruction rate (inst/s)
host_op_rate 254797 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 171091237 # Simulator tick rate (ticks/s)
host_mem_usage 314716 # Number of bytes of host memory used
host_seconds 6530.82 # Real time elapsed on the host
sim_insts 1544563088 # Number of instructions simulated
sim_ops 1664032481 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 50752 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 130973248 # Number of bytes read from this memory
system.physmem.bytes_read::total 131024000 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 50752 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 50752 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67225152 # Number of bytes written to this memory
system.physmem.bytes_written::total 67225152 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 793 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2046457 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2047250 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1050393 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1050393 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 45421 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 117216133 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 117261554 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 45421 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 45421 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 60163984 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 60163984 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 60163984 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 45421 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 117216133 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 177425537 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 2047250 # Number of read requests accepted
system.physmem.writeReqs 1050393 # Number of write requests accepted
system.physmem.readBursts 2047250 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1050393 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 130939136 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 84864 # Total number of bytes read from write queue
system.physmem.bytesWritten 67223488 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 131024000 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 67225152 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1326 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 127156 # Per bank write bursts
system.physmem.perBankRdBursts::1 124552 # Per bank write bursts
system.physmem.perBankRdBursts::2 121687 # Per bank write bursts
system.physmem.perBankRdBursts::3 123679 # Per bank write bursts
system.physmem.perBankRdBursts::4 122821 # Per bank write bursts
system.physmem.perBankRdBursts::5 122785 # Per bank write bursts
system.physmem.perBankRdBursts::6 123231 # Per bank write bursts
system.physmem.perBankRdBursts::7 123758 # Per bank write bursts
system.physmem.perBankRdBursts::8 131446 # Per bank write bursts
system.physmem.perBankRdBursts::9 133531 # Per bank write bursts
system.physmem.perBankRdBursts::10 132174 # Per bank write bursts
system.physmem.perBankRdBursts::11 133285 # Per bank write bursts
system.physmem.perBankRdBursts::12 133312 # Per bank write bursts
system.physmem.perBankRdBursts::13 133367 # Per bank write bursts
system.physmem.perBankRdBursts::14 129415 # Per bank write bursts
system.physmem.perBankRdBursts::15 129725 # Per bank write bursts
system.physmem.perBankWrBursts::0 66071 # Per bank write bursts
system.physmem.perBankWrBursts::1 64336 # Per bank write bursts
system.physmem.perBankWrBursts::2 62582 # Per bank write bursts
system.physmem.perBankWrBursts::3 63010 # Per bank write bursts
system.physmem.perBankWrBursts::4 63074 # Per bank write bursts
system.physmem.perBankWrBursts::5 63174 # Per bank write bursts
system.physmem.perBankWrBursts::6 64441 # Per bank write bursts
system.physmem.perBankWrBursts::7 65447 # Per bank write bursts
system.physmem.perBankWrBursts::8 67324 # Per bank write bursts
system.physmem.perBankWrBursts::9 67820 # Per bank write bursts
system.physmem.perBankWrBursts::10 67591 # Per bank write bursts
system.physmem.perBankWrBursts::11 67884 # Per bank write bursts
system.physmem.perBankWrBursts::12 67359 # Per bank write bursts
system.physmem.perBankWrBursts::13 67795 # Per bank write bursts
system.physmem.perBankWrBursts::14 66531 # Per bank write bursts
system.physmem.perBankWrBursts::15 65928 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 1117365281000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 2047250 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1050393 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1917221 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 128684 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 32675 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 33900 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 56925 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 61237 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 61674 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 61693 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 61618 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 61674 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 61673 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 61702 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 61770 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 61700 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 62209 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 62635 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 62095 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 62596 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 61333 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 61164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1911200 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 103.683951 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 81.827915 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 125.443095 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 1486351 77.77% 77.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 305207 15.97% 93.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 52508 2.75% 96.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 21149 1.11% 97.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 13340 0.70% 98.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 7581 0.40% 98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 5505 0.29% 98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5122 0.27% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 14437 0.76% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1911200 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 61162 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 33.403649 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 159.275472 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 61115 99.92% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 22 0.04% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 61162 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 61162 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.173523 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.138356 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.100510 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 27168 44.42% 44.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 1036 1.69% 46.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 28675 46.88% 93.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 3829 6.26% 99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 390 0.64% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 50 0.08% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 9 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 61162 # Writes before turning the bus around for reads
system.physmem.totQLat 38200049000 # Total ticks spent queuing
system.physmem.totMemAccLat 76561124000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 10229620000 # Total ticks spent in databus transfers
system.physmem.avgQLat 18671.29 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 37421.29 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 117.19 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 60.16 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 117.26 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 60.16 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.39 # Data bus utilization in percentage
system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing
system.physmem.readRowHits 773325 # Number of row buffer hits during reads
system.physmem.writeRowHits 411756 # Number of row buffer hits during writes
system.physmem.readRowHitRate 37.80 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 39.20 # Row buffer hit rate for writes
system.physmem.avgGap 360714.67 # Average gap between requests
system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 7043954400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3843427500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 7719106200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3318634800 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 72980394240 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 421878506670 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 300346094250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 817130118060 # Total energy per rank (pJ)
system.physmem_0.averagePower 731.305386 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 496942671500 # Time in different power states
system.physmem_0.memoryStateTime::REF 37311040000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 583108431500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 7404702480 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 4040264250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 8238734400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3487743360 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 72980394240 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 429447905460 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 293706270750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 819306014940 # Total energy per rank (pJ)
system.physmem_1.averagePower 733.252744 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 485853174500 # Time in different power states
system.physmem_1.memoryStateTime::REF 37311040000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 594197830000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 239770012 # Number of BP lookups
system.cpu.branchPred.condPredicted 186474623 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 14592511 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 129773424 # Number of BTB lookups
system.cpu.branchPred.BTBHits 122091028 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 94.080147 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 15653619 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 2234730749 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1544563088 # Number of instructions committed
system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed
system.cpu.discardedOps 41613452 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.446837 # CPI: cycles per instruction
system.cpu.ipc 0.691163 # IPC: instructions per cycle
system.cpu.tickCycles 1834912752 # Number of cycles that the object actually ticked
system.cpu.idleCycles 399817997 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 9221614 # number of replacements
system.cpu.dcache.tags.tagsinuse 4085.621118 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 624237491 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9225710 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 67.662813 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4085.621118 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997466 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997466 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1229 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1276880692 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1276880692 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 453906230 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 453906230 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170331138 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 170331138 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 624237368 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 624237368 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 624237369 # number of overall hits
system.cpu.dcache.overall_hits::total 624237369 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7335089 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7335089 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2254909 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2254909 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 9589998 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9589998 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9590000 # number of overall misses
system.cpu.dcache.overall_misses::total 9590000 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 191000565000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 191000565000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 109144177000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 109144177000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 300144742000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 300144742000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 300144742000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 300144742000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 461241319 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 461241319 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 633827366 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 633827366 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 633827369 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 633827369 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015903 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.015903 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013065 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013065 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26039.297546 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26039.297546 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48402.918699 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48402.918699 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31297.685568 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31297.685568 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31297.679041 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31297.679041 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3684549 # number of writebacks
system.cpu.dcache.writebacks::total 3684549 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364078 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 364078 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 364289 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 364289 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 364289 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 364289 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334878 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7334878 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890831 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1890831 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9225709 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9225709 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9225710 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9225710 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183660145000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 183660145000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84822237000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84822237000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268482382000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 268482382000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268482456000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 268482456000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014556 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014556 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014556 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014556 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25039.291042 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25039.291042 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44859.766420 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44859.766420 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29101.544608 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29101.544608 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29101.549474 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29101.549474 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 32 # number of replacements
system.cpu.icache.tags.tagsinuse 663.200919 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 465452181 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 826 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 563501.429782 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 663.200919 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.323829 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.323829 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 794 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 756 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.387695 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 930906840 # Number of tag accesses
system.cpu.icache.tags.data_accesses 930906840 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 465452181 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 465452181 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 465452181 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 465452181 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 465452181 # number of overall hits
system.cpu.icache.overall_hits::total 465452181 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 826 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 826 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 826 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 826 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 826 # number of overall misses
system.cpu.icache.overall_misses::total 826 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 62820500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 62820500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 62820500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 62820500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 62820500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 62820500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 465453007 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 465453007 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 465453007 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 465453007 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 465453007 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76053.874092 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76053.874092 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76053.874092 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76053.874092 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76053.874092 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76053.874092 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 826 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 826 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 826 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 826 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 826 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61994500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 61994500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61994500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 61994500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61994500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 61994500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75053.874092 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75053.874092 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75053.874092 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 75053.874092 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75053.874092 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75053.874092 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 2014550 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31258.830192 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14509707 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2044325 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 7.097554 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 59776132000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14827.946363 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.755718 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 16404.128111 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.452513 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000817 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.500614 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.953944 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 151507860 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 151507860 # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks 3684549 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3684549 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1089532 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1089532 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 32 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 32 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089717 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6089717 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7179249 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7179281 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7179249 # number of overall hits
system.cpu.l2cache.overall_hits::total 7179281 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 801299 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 801299 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 794 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 794 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1245162 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1245162 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 794 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2046461 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2047255 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 794 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2046461 # number of overall misses
system.cpu.l2cache.overall_misses::total 2047255 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70488254000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 70488254000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 60418000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 60418000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108710111500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 108710111500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 60418000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 179198365500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 179258783500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 60418000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 179198365500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 179258783500 # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks 3684549 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3684549 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890831 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1890831 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 826 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 826 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7334879 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 7334879 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 826 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9225710 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9226536 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 826 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9225710 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9226536 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423781 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.423781 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.961259 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.961259 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169759 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169759 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961259 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.221822 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.221888 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961259 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.221822 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.221888 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87967.480304 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87967.480304 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76093.198992 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76093.198992 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87305.998336 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87305.998336 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76093.198992 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87565.003926 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 87560.554743 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76093.198992 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87565.003926 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 87560.554743 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1050393 # number of writebacks
system.cpu.l2cache.writebacks::total 1050393 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 246 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 246 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801299 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 801299 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 793 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 793 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1245158 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1245158 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 793 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2046457 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2047250 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 793 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2046457 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2047250 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62475264000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62475264000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52472500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52472500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96258268000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96258268000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52472500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158733532000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 158786004500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52472500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158733532000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 158786004500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423781 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423781 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.960048 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.960048 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169758 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169758 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960048 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221821 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.221887 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960048 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221821 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.221887 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77967.480304 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77967.480304 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66169.609079 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66169.609079 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77306.067182 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77306.067182 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66169.609079 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77565.046322 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77560.632312 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66169.609079 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77565.046322 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77560.632312 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 7335705 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 4734942 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6499660 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1890831 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1890831 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 826 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334879 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1684 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671440 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27673124 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52864 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826256576 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 826309440 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 2014550 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 20462732 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.098450 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.297922 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 18448182 90.16% 90.16% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 2014550 9.84% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 20462732 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12908640000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1239499 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13838566996 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 1245951 # Transaction distribution
system.membus.trans_dist::Writeback 1050393 # Transaction distribution
system.membus.trans_dist::CleanEvict 963109 # Transaction distribution
system.membus.trans_dist::ReadExReq 801299 # Transaction distribution
system.membus.trans_dist::ReadExResp 801299 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1245951 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6108002 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 6108002 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198249152 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 198249152 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 4060752 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 4060752 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 4060752 # Request fanout histogram
system.membus.reqLayer0.occupancy 8665729500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 11195509250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
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