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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
Andreas Hansson 25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes 
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.846047 # Number of seconds simulated
sim_ticks 2846047385500 # Number of ticks simulated
final_tick 2846047385500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 159625 # Simulator instruction rate (inst/s)
host_op_rate 193311 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3563510303 # Simulator tick rate (ticks/s)
host_mem_usage 654020 # Number of bytes of host memory used
host_seconds 798.66 # Real time elapsed on the host
sim_insts 127487011 # Number of instructions simulated
sim_ops 154390534 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 7424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1468992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1221616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8255360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 381888 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 706136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 588160 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 12633224 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1468992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 381888 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1850880 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8928128 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 8945692 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 116 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 22953 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 19610 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 128990 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 5967 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 11055 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 9190 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 197938 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 139502 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 143893 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 2609 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 516152 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 429232 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 2900640 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 899 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 134182 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 248111 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 206659 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4438866 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 516152 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 134182 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 650334 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3137027 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3143199 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3137027 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 2609 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 516152 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 435390 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 2900640 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 899 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 134182 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 248125 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 206659 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7582065 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 197938 # Number of read requests accepted
system.physmem.writeReqs 143893 # Number of write requests accepted
system.physmem.readBursts 197938 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 143893 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12658432 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue
system.physmem.bytesWritten 8958080 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12633224 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8945692 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 51249 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 12124 # Per bank write bursts
system.physmem.perBankRdBursts::1 12298 # Per bank write bursts
system.physmem.perBankRdBursts::2 12956 # Per bank write bursts
system.physmem.perBankRdBursts::3 12344 # Per bank write bursts
system.physmem.perBankRdBursts::4 15465 # Per bank write bursts
system.physmem.perBankRdBursts::5 12573 # Per bank write bursts
system.physmem.perBankRdBursts::6 12691 # Per bank write bursts
system.physmem.perBankRdBursts::7 13082 # Per bank write bursts
system.physmem.perBankRdBursts::8 12243 # Per bank write bursts
system.physmem.perBankRdBursts::9 12357 # Per bank write bursts
system.physmem.perBankRdBursts::10 11723 # Per bank write bursts
system.physmem.perBankRdBursts::11 11147 # Per bank write bursts
system.physmem.perBankRdBursts::12 12049 # Per bank write bursts
system.physmem.perBankRdBursts::13 11871 # Per bank write bursts
system.physmem.perBankRdBursts::14 11344 # Per bank write bursts
system.physmem.perBankRdBursts::15 11521 # Per bank write bursts
system.physmem.perBankWrBursts::0 8574 # Per bank write bursts
system.physmem.perBankWrBursts::1 8801 # Per bank write bursts
system.physmem.perBankWrBursts::2 9504 # Per bank write bursts
system.physmem.perBankWrBursts::3 8801 # Per bank write bursts
system.physmem.perBankWrBursts::4 8786 # Per bank write bursts
system.physmem.perBankWrBursts::5 8838 # Per bank write bursts
system.physmem.perBankWrBursts::6 9085 # Per bank write bursts
system.physmem.perBankWrBursts::7 9267 # Per bank write bursts
system.physmem.perBankWrBursts::8 8941 # Per bank write bursts
system.physmem.perBankWrBursts::9 8908 # Per bank write bursts
system.physmem.perBankWrBursts::10 8524 # Per bank write bursts
system.physmem.perBankWrBursts::11 8283 # Per bank write bursts
system.physmem.perBankWrBursts::12 8972 # Per bank write bursts
system.physmem.perBankWrBursts::13 8287 # Per bank write bursts
system.physmem.perBankWrBursts::14 8306 # Per bank write bursts
system.physmem.perBankWrBursts::15 8093 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 26 # Number of times write queue was full causing retry
system.physmem.totGap 2846046899000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 554 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 197356 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 139502 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 97008 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 48975 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 12438 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 9719 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7811 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 6380 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 5314 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 4715 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3822 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 751 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 280 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 267 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 162 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2733 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4836 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5514 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6014 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6576 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6962 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8832 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 10148 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9569 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9515 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8822 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 9294 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 10498 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8607 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8058 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7671 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 489 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 332 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 297 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 187 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 153 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 158 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 90544 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 238.739707 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 135.462322 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 300.134416 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 48559 53.63% 53.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17642 19.48% 73.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6276 6.93% 80.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3581 3.95% 84.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2857 3.16% 87.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1437 1.59% 88.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 927 1.02% 89.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1107 1.22% 90.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8158 9.01% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 90544 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6994 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.279525 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 555.958801 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6993 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6994 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6994 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.012868 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.560049 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.293161 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5872 83.96% 83.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 361 5.16% 89.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 205 2.93% 92.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 59 0.84% 92.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 60 0.86% 93.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 157 2.24% 96.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 22 0.31% 96.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 8 0.11% 96.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 14 0.20% 96.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 7 0.10% 96.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 6 0.09% 96.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 8 0.11% 96.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 162 2.32% 99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 3 0.04% 99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 7 0.10% 99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 9 0.13% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 3 0.04% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.01% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.01% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.01% 99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 1 0.01% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.01% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 12 0.17% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 2 0.03% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 3 0.04% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 6 0.09% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 2 0.03% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6994 # Writes before turning the bus around for reads
system.physmem.totQLat 5635724944 # Total ticks spent queuing
system.physmem.totMemAccLat 9344249944 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 988940000 # Total ticks spent in databus transfers
system.physmem.avgQLat 28493.77 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 47243.77 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.15 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.14 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing
system.physmem.readRowHits 164502 # Number of row buffer hits during reads
system.physmem.writeRowHits 82711 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.17 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 59.08 # Row buffer hit rate for writes
system.physmem.avgGap 8325888.81 # Average gap between requests
system.physmem.pageHitRate 73.19 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 356257440 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 194386500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 807557400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 464330880 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 185889868320 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 83150566875 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1634688457500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1905551424915 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.543458 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2719326804644 # Time in different power states
system.physmem_0.memoryStateTime::REF 95035720000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 31683407856 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 328255200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 179107500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 735181200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 442674720 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 185889868320 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 82066427730 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1635639456750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1905280971420 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.448430 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2720915660225 # Time in different power states
system.physmem_1.memoryStateTime::REF 95035720000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 30095909775 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 19568417 # Number of BP lookups
system.cpu0.branchPred.condPredicted 12741959 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 982246 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 12413476 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 8819135 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 71.044847 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 3284365 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 198035 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 67683 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 67683 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45041 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22642 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples 67683 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 67683 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 67683 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 6748 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 10568.612922 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 9555.209008 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 5781.304513 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 6579 97.50% 97.50% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 156 2.31% 99.81% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 6748 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 327753000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 327753000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 327753000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5177 76.72% 76.72% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1571 23.28% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6748 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67683 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67683 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6748 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6748 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 74431 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 16473000 # DTB read hits
system.cpu0.dtb.read_misses 62137 # DTB read misses
system.cpu0.dtb.write_hits 13870452 # DTB write hits
system.cpu0.dtb.write_misses 5546 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3508 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1130 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 1591 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 16535137 # DTB read accesses
system.cpu0.dtb.write_accesses 13875998 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 30343452 # DTB hits
system.cpu0.dtb.misses 67683 # DTB misses
system.cpu0.dtb.accesses 30411135 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 3854 # Table walker walks requested
system.cpu0.itb.walker.walksShort 3854 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3547 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 3854 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 3854 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 3854 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2418 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 10984.077750 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 9918.433232 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 7783.469031 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767 2416 99.92% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2418 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 327059500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 327059500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 327059500 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2118 87.59% 87.59% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 300 12.41% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2418 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3854 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3854 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2418 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2418 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 6272 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 36667532 # ITB inst hits
system.cpu0.itb.inst_misses 3854 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2221 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 7326 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 36671386 # ITB inst accesses
system.cpu0.itb.hits 36667532 # DTB hits
system.cpu0.itb.misses 3854 # DTB misses
system.cpu0.itb.accesses 36671386 # DTB accesses
system.cpu0.numCycles 154642199 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 75578579 # Number of instructions committed
system.cpu0.committedOps 90977347 # Number of ops (including micro ops) committed
system.cpu0.discardedOps 4937651 # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends 2060 # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles 5537489017 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi 2.046111 # CPI: cycles per instruction
system.cpu0.ipc 0.488732 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 2062 # number of quiesce instructions executed
system.cpu0.tickCycles 120829876 # Number of cycles that the object actually ticked
system.cpu0.idleCycles 33812323 # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements 679563 # number of replacements
system.cpu0.dcache.tags.tagsinuse 486.133146 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 28909958 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 680075 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 42.509956 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 345411000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.133146 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949479 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.949479 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 60679422 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 60679422 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 14995018 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 14995018 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 12788335 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 12788335 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306891 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 306891 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 356622 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 356622 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352102 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 352102 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 27783353 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 27783353 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 28090244 # number of overall hits
system.cpu0.dcache.overall_hits::total 28090244 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 441719 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 441719 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 557349 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 557349 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131939 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 131939 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21205 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 21205 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21309 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 21309 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 999068 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 999068 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1131007 # number of overall misses
system.cpu0.dcache.overall_misses::total 1131007 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5838844500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5838844500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8827018500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 8827018500 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 323291000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 323291000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 480994000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 480994000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 412000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 412000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 14665863000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 14665863000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 14665863000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 14665863000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 15436737 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 15436737 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 13345684 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 13345684 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438830 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 438830 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 377827 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 377827 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373411 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 373411 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 28782421 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 28782421 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 29221251 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 29221251 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028615 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.028615 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041762 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.041762 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300661 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300661 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056124 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056124 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.057066 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.057066 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034711 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.034711 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038705 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.038705 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13218.459020 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13218.459020 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15837.506661 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15837.506661 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15245.979722 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15245.979722 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22572.340326 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22572.340326 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14679.544335 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14679.544335 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12967.084200 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12967.084200 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 493293 # number of writebacks
system.cpu0.dcache.writebacks::total 493293 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69842 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 69842 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 244235 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 244235 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15018 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15018 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 314077 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 314077 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 314077 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 314077 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371877 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 371877 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 313114 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 313114 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99356 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 99356 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6187 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6187 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21309 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 21309 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 684991 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 684991 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 784347 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 784347 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 18002 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18002 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16758 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16758 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34760 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34760 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4380232500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4380232500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4918203500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4918203500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1623471000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1623471000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94288500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94288500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459695000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459695000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 402000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 402000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9298436000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 9298436000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10921907000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10921907000 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3751545500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3751545500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2725656000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725656000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6477201500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6477201500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024090 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024090 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023462 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023462 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226411 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226411 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016375 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016375 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057066 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057066 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023799 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023799 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026842 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026842 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11778.713123 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11778.713123 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15707.389321 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15707.389321 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16339.939209 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16339.939209 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15239.776952 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15239.776952 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21572.809611 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21572.809611 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13574.537476 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13574.537476 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13924.840664 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13924.840664 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208396.039329 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208396.039329 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162648.048693 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162648.048693 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186340.664557 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186340.664557 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1878063 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.785549 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 34781277 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1878575 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 18.514713 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6156628000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.785549 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999581 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999581 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 75198332 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 75198332 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 34781277 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 34781277 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 34781277 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 34781277 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 34781277 # number of overall hits
system.cpu0.icache.overall_hits::total 34781277 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1878593 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1878593 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1878593 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1878593 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1878593 # number of overall misses
system.cpu0.icache.overall_misses::total 1878593 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17494191500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 17494191500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 17494191500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 17494191500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 17494191500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 17494191500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 36659870 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 36659870 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 36659870 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 36659870 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 36659870 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 36659870 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051244 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.051244 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051244 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.051244 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051244 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.051244 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9312.390443 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9312.390443 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9312.390443 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9312.390443 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9312.390443 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9312.390443 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1878593 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1878593 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1878593 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1878593 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1878593 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1878593 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 3426 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 3426 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16554895500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 16554895500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16554895500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 16554895500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16554895500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 16554895500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 314279000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 314279000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 314279000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 314279000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051244 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051244 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051244 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.051244 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051244 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.051244 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8812.390709 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8812.390709 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8812.390709 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 8812.390709 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8812.390709 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 8812.390709 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1765882 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1765970 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 77 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 224118 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 286262 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16059.277635 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 4797112 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 302498 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 15.858326 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 8723.236364 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 43.341002 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.066911 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4602.822845 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1559.466000 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1130.344513 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.532424 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002645 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.280934 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.095182 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068991 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.980181 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1044 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 15 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15177 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 332 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 429 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 270 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4328 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7768 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2750 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063721 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.926331 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 85339399 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 85339399 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80048 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4433 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 84481 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 493290 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 493290 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28251 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 28251 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1773 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 1773 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213027 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 213027 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1814336 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 1814336 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376020 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 376020 # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80048 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4433 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1814336 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 589047 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 2487864 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80048 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4433 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1814336 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 589047 # number of overall hits
system.cpu0.l2cache.overall_hits::total 2487864 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 723 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 114 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 837 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27851 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 27851 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19535 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 19535 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43989 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 43989 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 64257 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 64257 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101397 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 101397 # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 723 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 114 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 64257 # number of demand (read+write) misses
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system.cpu0.l2cache.demand_misses::total 210480 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 723 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 114 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 64257 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 145386 # number of overall misses
system.cpu0.l2cache.overall_misses::total 210480 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 24794500 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2781500 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 27576000 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 513504000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 513504000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 395434500 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 395434500 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 385999 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 385999 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2149567499 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 2149567499 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2872366000 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2872366000 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2916301996 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2916301996 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 24794500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2781500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2872366000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 5065869495 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 7965811495 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 24794500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2781500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2872366000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 5065869495 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 7965811495 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 80771 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4547 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 85318 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 493290 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 493290 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56102 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 56102 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21308 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 21308 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257016 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 257016 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1878593 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 1878593 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477417 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 477417 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 80771 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4547 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1878593 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 734433 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 2698344 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 80771 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4547 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1878593 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 734433 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 2698344 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008951 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025071 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.009810 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.496435 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.496435 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.916792 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.916792 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.171153 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171153 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.034205 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.034205 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212387 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212387 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008951 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025071 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034205 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.197957 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.078003 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008951 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025071 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034205 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.197957 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.078003 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34293.914246 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24399.122807 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32946.236559 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18437.542638 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18437.542638 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20242.359867 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20242.359867 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 385999 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 385999 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48866.023301 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48866.023301 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44701.215432 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44701.215432 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28761.225638 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28761.225638 # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34293.914246 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24399.122807 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44701.215432 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34844.273142 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 37845.930706 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34293.914246 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24399.122807 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44701.215432 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34844.273142 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 37845.930706 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 68 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 196466 # number of writebacks
system.cpu0.l2cache.writebacks::total 196466 # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2877 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 2877 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 67 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 67 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 395 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 395 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 67 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3272 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 3339 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 67 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3272 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 3339 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 723 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 114 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 9399 # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total 9399 # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 235023 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 235023 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27851 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27851 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19535 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19535 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41112 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 41112 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 64190 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 64190 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101002 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101002 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 723 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 114 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 64190 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142114 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 207141 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 723 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 114 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 64190 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142114 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 235023 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 442164 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 18002 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 21428 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16758 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16758 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34760 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 38186 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 20456500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2097500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 22554000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14138051507 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14138051507 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 556929500 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 556929500 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 298503500 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 298503500 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 325999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 325999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1579585500 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1579585500 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2485678500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2485678500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2287922496 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2287922496 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 20456500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2097500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2485678500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3867507996 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 6375740496 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 20456500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2097500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2485678500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3867507996 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14138051507 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 20513792003 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 286870500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3607450000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3894320500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2599707500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2599707500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 286870500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6207157500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6494028000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008951 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025071 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009810 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.496435 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.496435 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.916792 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.916792 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159959 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159959 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034169 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034169 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211559 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211559 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008951 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025071 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034169 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193502 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076766 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008951 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025071 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034169 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193502 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163865 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26946.236559 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60156.033695 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60156.033695 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19996.750566 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19996.750566 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15280.445354 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15280.445354 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 325999 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 325999 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38421.519264 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38421.519264 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38723.765384 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38723.765384 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22652.249421 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22652.249421 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38723.765384 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27214.123844 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30779.712833 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38723.765384 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27214.123844 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60156.033695 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46394.080031 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200391.623153 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.803061 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155132.324860 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155132.324860 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178571.849827 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170063.059760 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 136409 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 2524037 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 16758 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 866064 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 2177189 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 293784 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 92828 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43742 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 114509 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 285377 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 271332 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1878593 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603707 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5608538 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2465365 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11948 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 171096 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 8256947 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120449152 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82718835 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18188 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 323084 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 203509259 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 1215113 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 6486372 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 1.185022 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.388316 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 5286248 81.50% 81.50% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 1200124 18.50% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 6486372 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 3193659992 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 113350499 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 2823287977 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 1167322846 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 7403495 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 90327994 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 20515510 # Number of BP lookups
system.cpu1.branchPred.condPredicted 7101066 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 968769 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 10637682 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 7757881 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 72.928303 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 8827818 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 689615 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 30617 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 30617 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22895 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7722 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 30617 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 30617 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 30617 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 2694 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 10773.014105 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 9833.978032 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 6170.794386 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 858 31.85% 31.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1697 62.99% 94.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 63 2.34% 97.18% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767 63 2.34% 99.52% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151 7 0.26% 99.78% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.81% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.15% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 2694 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 1565807264 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1565807264 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1565807264 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 2001 74.28% 74.28% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 693 25.72% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2694 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30617 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30617 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2694 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2694 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 33311 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 12131046 # DTB read hits
system.cpu1.dtb.read_misses 27925 # DTB read misses
system.cpu1.dtb.write_hits 7724726 # DTB write hits
system.cpu1.dtb.write_misses 2692 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 318 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 531 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 287 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 12158971 # DTB read accesses
system.cpu1.dtb.write_accesses 7727418 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 19855772 # DTB hits
system.cpu1.dtb.misses 30617 # DTB misses
system.cpu1.dtb.accesses 19886389 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 2297 # Table walker walks requested
system.cpu1.itb.walker.walksShort 2297 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 182 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2115 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 2297 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 2297 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 2297 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 10860.516934 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10080.267537 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 5206.907244 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191 274 24.42% 24.42% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383 814 72.55% 96.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575 4 0.36% 97.33% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767 27 2.41% 99.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151 2 0.18% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1565238764 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1565238764 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1565238764 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 953 84.94% 84.94% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 169 15.06% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2297 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2297 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 3419 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 41950603 # ITB inst hits
system.cpu1.itb.inst_misses 2297 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1160 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 1848 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 41952900 # ITB inst accesses
system.cpu1.itb.hits 41950603 # DTB hits
system.cpu1.itb.misses 2297 # DTB misses
system.cpu1.itb.accesses 41952900 # DTB accesses
system.cpu1.numCycles 125141481 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 51908432 # Number of instructions committed
system.cpu1.committedOps 63413187 # Number of ops (including micro ops) committed
system.cpu1.discardedOps 5363692 # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends 2715 # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles 5566331294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi 2.410812 # CPI: cycles per instruction
system.cpu1.ipc 0.414798 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed
system.cpu1.tickCycles 105428618 # Number of cycles that the object actually ticked
system.cpu1.idleCycles 19712863 # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements 231919 # number of replacements
system.cpu1.dcache.tags.tagsinuse 484.812111 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 19337078 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 232252 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 83.259038 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 90437090000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.812111 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.946899 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.946899 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 333 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 279 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 54 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.650391 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 39720944 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 39720944 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 11670097 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 11670097 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 7386354 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 7386354 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 66295 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 66295 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88787 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 88787 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80732 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 80732 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 19056451 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 19056451 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 19122746 # number of overall hits
system.cpu1.dcache.overall_hits::total 19122746 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 184750 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 184750 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 167503 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 167503 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35001 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 35001 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17741 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 17741 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23478 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23478 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 352253 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 352253 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 387254 # number of overall misses
system.cpu1.dcache.overall_misses::total 387254 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2719987000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 2719987000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4150031500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 4150031500 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326839500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 326839500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548823500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 548823500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 416500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 416500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 6870018500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 6870018500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 6870018500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 6870018500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 11854847 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 11854847 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 7553857 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 7553857 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101296 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 101296 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106528 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 106528 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104210 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 104210 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 19408704 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 19408704 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 19510000 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 19510000 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.015584 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.015584 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.022174 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.022174 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.345532 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.345532 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.166538 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.166538 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225295 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225295 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.018149 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.018149 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019849 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.019849 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14722.527740 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14722.527740 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24775.863716 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 24775.863716 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18422.834113 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18422.834113 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23376.075475 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23376.075475 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19503.080172 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19503.080172 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17740.342256 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17740.342256 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 138789 # number of writebacks
system.cpu1.dcache.writebacks::total 138789 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18309 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 18309 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62144 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 62144 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12262 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12262 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 80453 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 80453 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 80453 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 80453 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166441 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 166441 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105359 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 105359 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33489 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 33489 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5479 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5479 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23478 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23478 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 271800 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 271800 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 305289 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 305289 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17142 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17142 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14413 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14413 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31555 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31555 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2292018500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2292018500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2517101000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2517101000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 540422500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 540422500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93861500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93861500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 525354500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 525354500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 407500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 407500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4809119500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4809119500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5349542000 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 5349542000 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2935336500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2935336500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2447202500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2447202500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5382539000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5382539000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014040 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014040 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013948 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013948 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.330605 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.330605 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051432 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051432 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225295 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225295 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014004 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.014004 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015648 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.015648 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.756604 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.756604 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23890.707011 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23890.707011 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16137.313745 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16137.313745 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17131.137069 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17131.137069 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22376.458813 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22376.458813 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17693.596394 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17693.596394 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17522.878322 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17522.878322 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171236.524326 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171236.524326 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169791.334212 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169791.334212 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170576.422120 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170576.422120 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 1046573 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.334165 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 40901496 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 1047085 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 39.062250 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 72079197500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.334165 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975262 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975262 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 461 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 84944247 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 84944247 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 40901496 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 40901496 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 40901496 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 40901496 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 40901496 # number of overall hits
system.cpu1.icache.overall_hits::total 40901496 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 1047085 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 1047085 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 1047085 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 1047085 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 1047085 # number of overall misses
system.cpu1.icache.overall_misses::total 1047085 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9273780500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 9273780500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 9273780500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 9273780500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 9273780500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 9273780500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 41948581 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 41948581 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 41948581 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 41948581 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 41948581 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 41948581 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024961 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.024961 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024961 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.024961 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024961 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.024961 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8856.759957 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 8856.759957 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8856.759957 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 8856.759957 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8856.759957 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 8856.759957 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1047085 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 1047085 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 1047085 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 1047085 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 1047085 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 1047085 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 113 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 113 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8750238000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 8750238000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8750238000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 8750238000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8750238000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 8750238000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10154500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10154500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10154500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 10154500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024961 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024961 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024961 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.024961 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024961 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.024961 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8356.759957 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8356.759957 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8356.759957 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 8356.759957 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8356.759957 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 8356.759957 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89862.831858 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89862.831858 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89862.831858 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89862.831858 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 270311 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 270335 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 70297 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 69395 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15632.228782 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 2434679 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 84293 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 28.883525 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 6105.214353 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.591846 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.935526 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5648.623425 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2320.323151 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1496.540481 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.372633 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003698 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000057 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.344765 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.141621 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.091342 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.954116 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1218 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13618 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 684 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 526 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 28 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6069 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7234 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074341 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003784 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.831177 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 43042452 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 43042452 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 33942 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2703 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 36645 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 138788 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 138788 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2017 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 2017 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1035 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 1035 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37928 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 37928 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 1019439 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 1019439 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 131721 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 131721 # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 33942 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2703 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 1019439 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 169649 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 1225733 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 33942 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2703 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 1019439 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 169649 # number of overall hits
system.cpu1.l2cache.overall_hits::total 1225733 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 703 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 221 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 924 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29293 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 29293 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22443 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 22443 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36124 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 36124 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 27646 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 27646 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73685 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 73685 # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 703 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 221 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 27646 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 109809 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 138379 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 703 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 221 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 27646 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 109809 # number of overall misses
system.cpu1.l2cache.overall_misses::total 138379 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 17833500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4520500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 22354000 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 553092500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 553092500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 450276000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 450276000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 393500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 393500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1418705500 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1418705500 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1071948000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1071948000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1752324498 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1752324498 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 17833500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4520500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1071948000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 3171029998 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 4265331998 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 17833500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4520500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1071948000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 3171029998 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 4265331998 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 34645 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2924 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 37569 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 138788 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 138788 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31310 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 31310 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23478 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23478 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 74052 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 74052 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 1047085 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 1047085 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 205406 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 205406 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 34645 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2924 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 1047085 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 279458 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 1364112 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 34645 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2924 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 1047085 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 279458 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 1364112 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020292 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.075581 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.024595 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.935580 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.935580 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.955916 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.955916 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.487819 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.487819 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026403 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026403 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.358729 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.358729 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020292 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.075581 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026403 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.392936 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.101443 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020292 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.075581 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026403 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.392936 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.101443 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25367.709815 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20454.751131 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24192.640693 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18881.388045 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18881.388045 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20063.093169 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20063.093169 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39273.211715 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39273.211715 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38774.072199 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38774.072199 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23781.291959 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23781.291959 # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25367.709815 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20454.751131 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38774.072199 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28877.687603 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 30823.549802 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25367.709815 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20454.751131 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38774.072199 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28877.687603 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 30823.549802 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 36782 # number of writebacks
system.cpu1.l2cache.writebacks::total 36782 # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 330 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 330 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 21 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 21 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 131 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 131 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 21 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 461 # number of demand (read+write) MSHR hits
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system.cpu1.l2cache.overall_mshr_hits::cpu1.data 461 # number of overall MSHR hits
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system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 703 # number of ReadReq MSHR misses
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system.cpu1.l2cache.ReadReq_mshr_misses::total 924 # number of ReadReq MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 3084 # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total 3084 # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35155 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 35155 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29293 # number of UpgradeReq MSHR misses
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system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22443 # number of SCUpgradeReq MSHR misses
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system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 27625 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 109348 # number of demand (read+write) MSHR misses
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system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17142 # number of ReadReq MSHR uncacheable
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system.cpu1.l2cache.overall_mshr_miss_latency::total 4681963045 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9250500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2798164000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2807414500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2338978500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2338978500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9250500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5137142500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5146393000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020292 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.075581 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.024595 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.935580 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.935580 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955916 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955916 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.483363 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.483363 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026383 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026383 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.358091 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.358091 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020292 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.075581 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026383 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.391286 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101089 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020292 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.075581 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026383 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.391286 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.126861 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18192.640693 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36634.064770 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36634.064770 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17117.161062 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17117.161062 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15518.669518 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15518.669518 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32552.159580 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32552.159580 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32780.923077 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32780.923077 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17762.970036 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17762.970036 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32780.923077 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22604.066814 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24613.243928 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32780.923077 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22604.066814 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36634.064770 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27055.237992 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81862.831858 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163234.395053 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162701.506810 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162282.557413 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162282.557413 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81862.831858 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162799.635557 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162510.831123 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 81434 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 1353329 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 14413 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 511562 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 1270278 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 44724 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 77037 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43004 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 89317 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 97290 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 79982 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1047085 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 561570 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3121460 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1041902 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7336 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 72984 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 4243682 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67020672 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29874703 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11696 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 138580 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 97045651 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 1176077 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 3823827 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 1.296126 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.456547 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 2691491 70.39% 70.39% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 1132336 29.61% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 3823827 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 1513117496 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 87426499 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 1570862868 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 471839695 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 4412000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 38355467 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 31014 # Transaction distribution
system.iobus.trans_dist::ReadResp 31014 # Transaction distribution
system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
system.iobus.trans_dist::WriteResp 59422 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 187550442 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36446 # number of replacements
system.iocache.tags.tagsinuse 14.479147 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36462 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 270355599000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.479147 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.904947 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.904947 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328320 # Number of tag accesses
system.iocache.tags.data_accesses 328320 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses
system.iocache.ReadReq_misses::total 256 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 256 # number of demand (read+write) misses
system.iocache.demand_misses::total 256 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 256 # number of overall misses
system.iocache.overall_misses::total 256 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 32686877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 32686877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4278417565 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4278417565 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 32686877 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 32686877 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 32686877 # number of overall miss cycles
system.iocache.overall_miss_latency::total 32686877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 256 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 256 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 256 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 256 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 127683.113281 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 127683.113281 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118110.025536 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118110.025536 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 127683.113281 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 127683.113281 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 127683.113281 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 127683.113281 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 5.250000 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 256 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 256 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 256 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 19886877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 19886877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2467217565 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2467217565 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 19886877 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 19886877 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 19886877 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 19886877 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77683.113281 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 77683.113281 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68110.025536 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68110.025536 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 77683.113281 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 77683.113281 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 77683.113281 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 77683.113281 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 135320 # number of replacements
system.l2c.tags.tagsinuse 64080.552826 # Cycle average of tags in use
system.l2c.tags.total_refs 445963 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 199765 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.232438 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 12788.353662 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.367527 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.034390 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 7205.553479 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2096.784928 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32107.700654 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 26.808299 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.851993 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 4024.713832 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1527.951308 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4232.432754 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.195135 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001058 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.109948 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.031994 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.489925 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000409 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000013 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.061412 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.023315 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064582 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.977792 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 29238 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 35135 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 5585 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 23534 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 72 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 3030 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 31767 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.446136 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.536118 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 5845545 # Number of tag accesses
system.l2c.tags.data_accesses 5845545 # Number of data accesses
system.l2c.Writeback_hits::writebacks 233248 # number of Writeback hits
system.l2c.Writeback_hits::total 233248 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3007 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 942 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 3949 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 254 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 81 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 335 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 4095 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 2177 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 6272 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 343 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 65 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 44646 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 47683 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46675 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 154 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 31 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 21738 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 11221 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8044 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 180600 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 343 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 65 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 44646 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 51778 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 46675 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 154 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 31 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 21738 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 13398 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 8044 # number of demand (read+write) hits
system.l2c.demand_hits::total 186872 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 343 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 65 # number of overall hits
system.l2c.overall_hits::cpu0.inst 44646 # number of overall hits
system.l2c.overall_hits::cpu0.data 51778 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 46675 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 154 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 31 # number of overall hits
system.l2c.overall_hits::cpu1.inst 21738 # number of overall hits
system.l2c.overall_hits::cpu1.data 13398 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 8044 # number of overall hits
system.l2c.overall_hits::total 186872 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 8773 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4095 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 12868 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 811 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1218 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2029 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 10812 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 8416 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 19228 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 116 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 19540 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 8519 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 129160 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 40 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 5871 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 2660 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 9190 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 175098 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 116 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 19540 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 19331 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 129160 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 40 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 5871 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 11076 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 9190 # number of demand (read+write) misses
system.l2c.demand_misses::total 194326 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 116 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.inst 19540 # number of overall misses
system.l2c.overall_misses::cpu0.data 19331 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 129160 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 40 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 5871 # number of overall misses
system.l2c.overall_misses::cpu1.data 11076 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 9190 # number of overall misses
system.l2c.overall_misses::total 194326 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 9401500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 5084500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 14486000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1177000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1665000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 2842000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 989600500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 687604500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1677205000 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 10015500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 303000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1567254000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 747042500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13330410791 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 3705500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 82500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 483609000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 234711500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1119629067 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 17496763358 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 10015500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 303000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 1567254000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 1736643000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13330410791 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 3705500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 82500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 483609000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 922316000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1119629067 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 19173968358 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 10015500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 303000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 1567254000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 1736643000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13330410791 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 3705500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 82500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 483609000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 922316000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1119629067 # number of overall miss cycles
system.l2c.overall_miss_latency::total 19173968358 # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks 233248 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 233248 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 11780 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5037 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 16817 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 1065 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 1299 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2364 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 14907 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 10593 # number of ReadExReq accesses(hits+misses)
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system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.overall_mshr_miss_latency::cpu1.inst 424750500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 811556000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1027729067 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 17230483358 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 214924500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3283407500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6877000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2489619500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 5994828500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2314728500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2093956000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 4408684500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 214924500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5598136000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6877000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4583575500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 10403513000 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.744737 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.812984 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.765178 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.761502 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.937644 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.858291 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.725297 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.794487 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.754039 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.252723 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.015152 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.304397 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.151578 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.734552 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.206186 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.031250 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.212503 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.191629 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533248 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.492249 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.252723 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.015152 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.304397 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.271850 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.734552 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.206186 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.031250 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.212503 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.452562 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533248 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.509761 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.252723 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.015152 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.304397 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.271850 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.734552 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.206186 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.031250 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.212503 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.452562 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533248 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.509761 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20855.807591 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20761.905006 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20825.924852 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20883.477189 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20769.293924 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20814.933465 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 81527.978172 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71702.055608 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 77227.220720 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70210.743167 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77691.337011 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 72500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72396.539969 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78237.406015 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 89927.343100 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70210.743167 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79837.204490 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72396.539969 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73271.578187 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 88670.663637 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70210.743167 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79837.204490 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72396.539969 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73271.578187 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 88670.663637 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.262082 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60858.407080 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145268.963706 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154989.231883 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138126.775272 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145282.453341 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141435.452825 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161051.093211 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60858.407080 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145275.125986 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 148940.773085 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 38679 # Transaction distribution
system.membus.trans_dist::ReadResp 214027 # Transaction distribution
system.membus.trans_dist::WriteReq 31171 # Transaction distribution
system.membus.trans_dist::WriteResp 31171 # Transaction distribution
system.membus.trans_dist::Writeback 139502 # Transaction distribution
system.membus.trans_dist::CleanEvict 18408 # Transaction distribution
system.membus.trans_dist::UpgradeReq 78648 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 41625 # Transaction distribution
system.membus.trans_dist::UpgradeResp 15041 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
system.membus.trans_dist::ReadExReq 39591 # Transaction distribution
system.membus.trans_dist::ReadExResp 19084 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 175348 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14764 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 682494 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 805212 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108922 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108922 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 914134 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29528 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19261796 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 19455462 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 21772582 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 126350 # Total snoops (count)
system.membus.snoop_fanout::samples 599467 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 599467 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 599467 # Request fanout histogram
system.membus.reqLayer0.occupancy 91393000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 24328 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 12942500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1014707988 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1166663343 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 64473559 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 38683 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 520875 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 31171 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 372774 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 100063 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 82453 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 41960 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 124413 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 51599 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 51599 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 482207 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1095171 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 404182 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1499353 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32852839 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6925951 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 39778790 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 466118 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 1289558 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.161505 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.367996 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 1081288 83.85% 83.85% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 208270 16.15% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 1289558 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 856703495 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 361500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 633166148 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 285761511 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
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