1330 lines
158 KiB
Text
1330 lines
158 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 5.194411 # Number of seconds simulated
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sim_ticks 5194410635000 # Number of ticks simulated
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final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1282120 # Simulator instruction rate (inst/s)
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host_op_rate 2471507 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 51858853246 # Simulator tick rate (ticks/s)
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host_mem_usage 594916 # Number of bytes of host memory used
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host_seconds 100.16 # Real time elapsed on the host
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sim_insts 128422722 # Number of instructions simulated
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sim_ops 247557000 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9099264 # Number of bytes read from this memory
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system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
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system.physmem.bytes_read::total 9957440 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 829440 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 829440 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 5149824 # Number of bytes written to this memory
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system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
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system.physmem.bytes_written::total 8139904 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 12960 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 142176 # Number of read requests responded to by this memory
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system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 155585 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 80466 # Number of write requests responded to by this memory
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system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 127186 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 159679 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1751741 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1916953 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 159679 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 159679 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 991416 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::pc.south_bridge.ide 575634 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1567051 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 991416 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 159679 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1751741 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3484003 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 155585 # Number of read requests accepted
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system.physmem.writeReqs 127186 # Number of write requests accepted
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system.physmem.readBursts 155585 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 127186 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 9942720 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 14720 # Total number of bytes read from write queue
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system.physmem.bytesWritten 8138624 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 9957440 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 8139904 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 230 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 1629 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 10087 # Per bank write bursts
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system.physmem.perBankRdBursts::1 9924 # Per bank write bursts
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system.physmem.perBankRdBursts::2 10111 # Per bank write bursts
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system.physmem.perBankRdBursts::3 9612 # Per bank write bursts
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system.physmem.perBankRdBursts::4 10046 # Per bank write bursts
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system.physmem.perBankRdBursts::5 9507 # Per bank write bursts
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system.physmem.perBankRdBursts::6 9544 # Per bank write bursts
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system.physmem.perBankRdBursts::7 9545 # Per bank write bursts
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system.physmem.perBankRdBursts::8 9177 # Per bank write bursts
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system.physmem.perBankRdBursts::9 9299 # Per bank write bursts
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system.physmem.perBankRdBursts::10 9268 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9485 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9621 # Per bank write bursts
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system.physmem.perBankRdBursts::13 9970 # Per bank write bursts
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system.physmem.perBankRdBursts::14 10158 # Per bank write bursts
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system.physmem.perBankRdBursts::15 10001 # Per bank write bursts
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system.physmem.perBankWrBursts::0 8060 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7801 # Per bank write bursts
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system.physmem.perBankWrBursts::2 7998 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7765 # Per bank write bursts
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system.physmem.perBankWrBursts::4 8116 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7896 # Per bank write bursts
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system.physmem.perBankWrBursts::6 7662 # Per bank write bursts
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system.physmem.perBankWrBursts::7 7717 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7519 # Per bank write bursts
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system.physmem.perBankWrBursts::9 7838 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7675 # Per bank write bursts
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system.physmem.perBankWrBursts::11 7654 # Per bank write bursts
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system.physmem.perBankWrBursts::12 8493 # Per bank write bursts
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system.physmem.perBankWrBursts::13 8626 # Per bank write bursts
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system.physmem.perBankWrBursts::14 8402 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7944 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
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system.physmem.totGap 5194410571500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 155585 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 127186 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 151951 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 2969 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 2364 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 3127 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 6124 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 6381 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 6410 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 7140 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 7424 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 8105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 8845 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 9948 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 9118 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 8439 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 7706 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 7452 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 6421 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 6193 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 6287 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 6139 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 216 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 191 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 191 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 204 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 214 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 184 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 176 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 181 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 61 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 47 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 55971 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 323.047292 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 191.702498 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 334.763320 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 19466 34.78% 34.78% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 13850 24.74% 59.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 5737 10.25% 69.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 3527 6.30% 76.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2331 4.16% 80.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1635 2.92% 83.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1137 2.03% 85.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 981 1.75% 86.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 7307 13.05% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 55971 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5932 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 26.188806 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::stdev 621.686791 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-2047 5931 99.98% 99.98% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::total 5932 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 5932 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 21.437289 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 19.381245 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::stdev 13.855005 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-19 4878 82.23% 82.23% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::20-23 44 0.74% 82.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 36 0.61% 83.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 295 4.97% 88.55% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 297 5.01% 93.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 20 0.34% 93.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 18 0.30% 94.20% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 14 0.24% 94.44% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 21 0.35% 94.79% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 5 0.08% 94.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 1 0.02% 94.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 3 0.05% 94.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 234 3.94% 98.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 3 0.05% 98.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 4 0.07% 99.01% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 4 0.07% 99.07% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 9 0.15% 99.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 12 0.20% 99.43% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 2 0.03% 99.46% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-107 5 0.08% 99.54% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 2 0.03% 99.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 8 0.13% 99.71% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::116-119 2 0.03% 99.75% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 10 0.17% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 3 0.05% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5932 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 1472209750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 4385116000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 776775000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 9476.42 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 28226.42 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 21.88 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 127796 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 98753 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 77.64 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 18369672.18 # Average gap between requests
|
|
system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 4972956663750 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 173452760000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 48001096250 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem.actEnergy::0 211543920 # Energy for activate commands per rank (pJ)
|
|
system.physmem.actEnergy::1 211596840 # Energy for activate commands per rank (pJ)
|
|
system.physmem.preEnergy::0 115425750 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.preEnergy::1 115454625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.readEnergy::0 611332800 # Energy for read commands per rank (pJ)
|
|
system.physmem.readEnergy::1 600428400 # Energy for read commands per rank (pJ)
|
|
system.physmem.writeEnergy::0 408337200 # Energy for write commands per rank (pJ)
|
|
system.physmem.writeEnergy::1 415698480 # Energy for write commands per rank (pJ)
|
|
system.physmem.refreshEnergy::0 339273598560 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.refreshEnergy::1 339273598560 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.actBackEnergy::0 134393532390 # Energy for active background per rank (pJ)
|
|
system.physmem.actBackEnergy::1 134240531850 # Energy for active background per rank (pJ)
|
|
system.physmem.preBackEnergy::0 2998756974750 # Energy for precharge background per rank (pJ)
|
|
system.physmem.preBackEnergy::1 2998891185750 # Energy for precharge background per rank (pJ)
|
|
system.physmem.totalEnergy::0 3473770745370 # Total energy per rank (pJ)
|
|
system.physmem.totalEnergy::1 3473748494505 # Total energy per rank (pJ)
|
|
system.physmem.averagePower::0 668.751736 # Core power per rank (mW)
|
|
system.physmem.averagePower::1 668.747452 # Core power per rank (mW)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
|
system.cpu.numCycles 10388821270 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 128422722 # Number of instructions committed
|
|
system.cpu.committedOps 247557000 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 232138334 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu.num_func_calls 2301199 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 23183159 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 232138334 # number of integer instructions
|
|
system.cpu.num_fp_insts 0 # number of float instructions
|
|
system.cpu.num_int_register_reads 434808798 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 197991574 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu.num_cc_register_reads 132893231 # number of times the CC registers were read
|
|
system.cpu.num_cc_register_writes 95600147 # number of times the CC registers were written
|
|
system.cpu.num_mem_refs 22258678 # number of memory refs
|
|
system.cpu.num_load_insts 13887993 # Number of load instructions
|
|
system.cpu.num_store_insts 8370685 # Number of store instructions
|
|
system.cpu.num_idle_cycles 9791802498.998116 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 597018771.001885 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.057467 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.942533 # Percentage of idle cycles
|
|
system.cpu.Branches 26323220 # Number of branches fetched
|
|
system.cpu.op_class::No_OpClass 174807 0.07% 0.07% # Class of executed instruction
|
|
system.cpu.op_class::IntAlu 224862012 90.83% 90.90% # Class of executed instruction
|
|
system.cpu.op_class::IntMult 139985 0.06% 90.96% # Class of executed instruction
|
|
system.cpu.op_class::IntDiv 123095 0.05% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdAlu 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdCmp 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdCvt 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdMisc 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdMult 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdShift 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction
|
|
system.cpu.op_class::MemRead 13887993 5.61% 96.62% # Class of executed instruction
|
|
system.cpu.op_class::MemWrite 8370685 3.38% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::total 247558577 # Class of executed instruction
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu.dcache.tags.replacements 1622351 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.996907 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 20038370 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1622863 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 12.347543 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.996907 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 8035174 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 8035174 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 59224 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 59224 # number of SoftPFReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 19976948 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 19976948 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 20036172 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 20036172 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 907115 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 907115 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 325077 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 325077 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 402500 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 402500 # number of SoftPFReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1232192 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1232192 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1634692 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1634692 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12725992750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 12725992750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11362158354 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 11362158354 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 24088151104 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 24088151104 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 24088151104 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 24088151104 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 12848889 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 12848889 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8360251 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 8360251 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461724 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 461724 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 21209140 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 21209140 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 21670864 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 21670864 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070599 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.070599 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038884 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871733 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.871733 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.058097 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.058097 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 19549.024100 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 14735.590010 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1538923 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 9252 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 9540 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 9540 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 9540 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 9540 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906827 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 906827 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315825 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 315825 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402464 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 402464 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1222652 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1222652 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1625116 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1625116 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10904887500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10904887500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10229869846 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10229869846 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337291000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337291000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21134757346 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 21134757346 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472048346 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 26472048346 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802063500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070576 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057647 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dtb_walker_cache.tags.replacements 7576 # number of replacements
|
|
system.cpu.dtb_walker_cache.tags.tagsinuse 5.056356 # Cycle average of tags in use
|
|
system.cpu.dtb_walker_cache.tags.total_refs 13259 # Total number of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.tags.sampled_refs 7591 # Sample count of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.tags.avg_refs 1.746674 # Average number of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.056356 # Average occupied blocks per requestor
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316022 # Average percentage of cache occupancy
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316022 # Average percentage of cache occupancy
|
|
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
|
|
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
|
|
system.cpu.dtb_walker_cache.tags.tag_accesses 52917 # Number of tag accesses
|
|
system.cpu.dtb_walker_cache.tags.data_accesses 52917 # Number of data accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13260 # number of ReadReq hits
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 13260 # number of ReadReq hits
|
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13260 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.demand_hits::total 13260 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13260 # number of overall hits
|
|
system.cpu.dtb_walker_cache.overall_hits::total 13260 # number of overall hits
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8799 # number of ReadReq misses
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 8799 # number of ReadReq misses
|
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8799 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.demand_misses::total 8799 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8799 # number of overall misses
|
|
system.cpu.dtb_walker_cache.overall_misses::total 8799 # number of overall misses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 94478000 # number of ReadReq miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 94478000 # number of ReadReq miss cycles
|
|
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 94478000 # number of demand (read+write) miss cycles
|
|
system.cpu.dtb_walker_cache.demand_miss_latency::total 94478000 # number of demand (read+write) miss cycles
|
|
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 94478000 # number of overall miss cycles
|
|
system.cpu.dtb_walker_cache.overall_miss_latency::total 94478000 # number of overall miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22059 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 22059 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22059 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 22059 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22059 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 22059 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398885 # miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398885 # miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398885 # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398885 # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398885 # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398885 # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518 # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518 # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dtb_walker_cache.writebacks::writebacks 3010 # number of writebacks
|
|
system.cpu.dtb_walker_cache.writebacks::total 3010 # number of writebacks
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8799 # number of ReadReq MSHR misses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8799 # number of ReadReq MSHR misses
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8799 # number of demand (read+write) MSHR misses
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses::total 8799 # number of demand (read+write) MSHR misses
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8799 # number of overall MSHR misses
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses::total 8799 # number of overall MSHR misses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76879500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 76879500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 76879500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 76879500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 76879500 # number of overall MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 76879500 # number of overall MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398885 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398885 # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398885 # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average ReadReq mshr miss latency
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8737.299693 # average ReadReq mshr miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 791372 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.348934 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 144679417 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 791884 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 182.702791 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 161114367250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.348934 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.996775 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.996775 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 146263199 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 146263199 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 144679417 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 144679417 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 144679417 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 144679417 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 144679417 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 144679417 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 791891 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 791891 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 791891 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 791891 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 791891 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 791891 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11123124618 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 11123124618 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 11123124618 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 11123124618 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 11123124618 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 11123124618 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 145471308 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 145471308 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 145471308 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 145471308 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 145471308 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 145471308 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005444 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.005444 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.005444 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.005444 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.005444 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.005444 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14046.282403 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 14046.282403 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14046.282403 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 14046.282403 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14046.282403 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 14046.282403 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791891 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 791891 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 791891 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 791891 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 791891 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 791891 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9534445382 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 9534445382 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9534445382 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 9534445382 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9534445382 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 9534445382 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005444 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.005444 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.005444 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12040.098173 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12040.098173 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12040.098173 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12040.098173 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12040.098173 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12040.098173 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.itb_walker_cache.tags.replacements 3756 # number of replacements
|
|
system.cpu.itb_walker_cache.tags.tagsinuse 3.071335 # Cycle average of tags in use
|
|
system.cpu.itb_walker_cache.tags.total_refs 7599 # Total number of references to valid blocks.
|
|
system.cpu.itb_walker_cache.tags.sampled_refs 3768 # Sample count of references to valid blocks.
|
|
system.cpu.itb_walker_cache.tags.avg_refs 2.016720 # Average number of references to valid blocks.
|
|
system.cpu.itb_walker_cache.tags.warmup_cycle 5167567118000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.071335 # Average occupied blocks per requestor
|
|
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191958 # Average percentage of cache occupancy
|
|
system.cpu.itb_walker_cache.tags.occ_percent::total 0.191958 # Average percentage of cache occupancy
|
|
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
|
|
system.cpu.itb_walker_cache.tags.tag_accesses 29071 # Number of tag accesses
|
|
system.cpu.itb_walker_cache.tags.data_accesses 29071 # Number of data accesses
|
|
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7599 # number of ReadReq hits
|
|
system.cpu.itb_walker_cache.ReadReq_hits::total 7599 # number of ReadReq hits
|
|
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
|
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
|
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7601 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.demand_hits::total 7601 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7601 # number of overall hits
|
|
system.cpu.itb_walker_cache.overall_hits::total 7601 # number of overall hits
|
|
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4623 # number of ReadReq misses
|
|
system.cpu.itb_walker_cache.ReadReq_misses::total 4623 # number of ReadReq misses
|
|
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4623 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.demand_misses::total 4623 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4623 # number of overall misses
|
|
system.cpu.itb_walker_cache.overall_misses::total 4623 # number of overall misses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 47504750 # number of ReadReq miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 47504750 # number of ReadReq miss cycles
|
|
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 47504750 # number of demand (read+write) miss cycles
|
|
system.cpu.itb_walker_cache.demand_miss_latency::total 47504750 # number of demand (read+write) miss cycles
|
|
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 47504750 # number of overall miss cycles
|
|
system.cpu.itb_walker_cache.overall_miss_latency::total 47504750 # number of overall miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12222 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::total 12222 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12224 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.demand_accesses::total 12224 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12224 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::total 12224 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.378252 # miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.378252 # miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.378190 # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::total 0.378190 # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.378190 # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::total 0.378190 # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10275.740861 # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10275.740861 # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10275.740861 # average overall miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10275.740861 # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10275.740861 # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10275.740861 # average overall miss latency
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.itb_walker_cache.writebacks::writebacks 825 # number of writebacks
|
|
system.cpu.itb_walker_cache.writebacks::total 825 # number of writebacks
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4623 # number of ReadReq MSHR misses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4623 # number of ReadReq MSHR misses
|
|
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4623 # number of demand (read+write) MSHR misses
|
|
system.cpu.itb_walker_cache.demand_mshr_misses::total 4623 # number of demand (read+write) MSHR misses
|
|
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4623 # number of overall MSHR misses
|
|
system.cpu.itb_walker_cache.overall_mshr_misses::total 4623 # number of overall MSHR misses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 38257250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 38257250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 38257250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 38257250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 38257250 # number of overall MSHR miss cycles
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 38257250 # number of overall MSHR miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.378252 # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.378252 # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.378190 # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.378190 # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.378190 # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.378190 # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average ReadReq mshr miss latency
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8275.416396 # average ReadReq mshr miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 87384 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 64746.924059 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 3489247 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 152088 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 22.942290 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 50375.433193 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006760 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141629 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3244.771000 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 11126.571476 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.768668 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049511 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.169778 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.987960 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64704 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2830 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4041 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57717 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987305 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 32214708 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 32214708 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6577 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3185 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 778918 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1279822 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2068502 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1542758 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1542758 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 199803 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 199803 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6577 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 3185 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 778918 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1479625 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2268305 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6577 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 3185 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 778918 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1479625 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2268305 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 12960 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 28635 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 41601 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1351 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 1351 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 113819 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 113819 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 12960 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 142454 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 155420 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 12960 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 142454 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 155420 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 350750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 953249250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2133765000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 3087454250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15012361 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 15012361 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7880712972 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 7880712972 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 350750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 953249250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10014477972 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 10968167222 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 350750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 953249250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10014477972 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 10968167222 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6578 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3190 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791878 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1308457 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2110103 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1542758 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1542758 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1672 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 1672 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 313622 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 313622 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6578 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3190 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 791878 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1622079 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2423725 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6578 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3190 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 791878 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1622079 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2423725 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000152 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001567 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016366 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021885 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.019715 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808014 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808014 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362918 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.362918 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000152 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001567 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016366 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.087822 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.064124 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000152 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001567 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016366 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087822 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.064124 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 70150 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73553.182870 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74515.976951 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74215.866205 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11112.036269 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11112.036269 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.993244 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.993244 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73553.182870 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70299.731647 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 70571.144138 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73553.182870 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70299.731647 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 70571.144138 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 80466 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 80466 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12960 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28635 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 41601 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1351 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1351 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113819 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 113819 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12960 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 142454 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 155420 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12960 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 142454 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 155420 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 790892250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1774999000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2566255250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13524351 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13524351 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6458128028 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6458128028 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 790892250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8233127028 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9024383278 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 790892250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8233127028 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9024383278 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86680074500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86680074500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2394893500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2394893500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89074968000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89074968000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021885 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019715 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808014 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808014 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362918 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362918 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087822 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.064124 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087822 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.064124 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61025.636574 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61987.043827 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.345256 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.622502 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.622502 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56740.333582 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56740.333582 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61025.636574 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57794.986648 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61025.636574 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57794.986648 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 313627 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 313627 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583769 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979028 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8638 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18387 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 7589822 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50680192 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203991823 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 613632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 255542607 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 52938 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 4020768 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3.011831 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.108123 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 3973200 98.82% 98.82% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 4020768 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 3834027500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1190285118 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3054401379 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 6935250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 13198750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 230267 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 230267 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 57693 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 57694 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution
|
|
system.iobus.trans_dist::MessageReq 1655 # Transaction distribution
|
|
system.iobus.trans_dist::MessageResp 1655 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 421906845 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 47512 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007386 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.007386 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 428111 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 428111 # Number of data accesses
|
|
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
|
|
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
|
|
system.iocache.ReadReq_misses::pc.south_bridge.ide 847 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 847 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 1 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::pc.south_bridge.ide 847 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 847 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::pc.south_bridge.ide 847 # number of overall misses
|
|
system.iocache.overall_misses::total 847 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141540186 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 141540186 # number of ReadReq miss cycles
|
|
system.iocache.demand_miss_latency::pc.south_bridge.ide 141540186 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 141540186 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::pc.south_bridge.ide 141540186 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 141540186 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::pc.south_bridge.ide 847 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46721 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 46721 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::pc.south_bridge.ide 847 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 847 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::pc.south_bridge.ide 847 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency
|
|
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 46720 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses
|
|
system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 624009 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 624009 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 13889 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 13889 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 80466 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 1629 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 113541 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 113541 # Transaction distribution
|
|
system.membus.trans_dist::MessageReq 1655 # Transaction distribution
|
|
system.membus.trans_dist::MessageResp 1655 # Transaction distribution
|
|
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710112 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394547 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1585447 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94730 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 94730 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1683487 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420221 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15078912 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16745807 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 943 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 285344 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 285344 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks)
|
|
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks)
|
|
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
|
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
|
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
|
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
|
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
|
|
|
---------- End Simulation Statistics ----------
|