98c94cfe3c
The necessary companion conversion of Ruby objects generated by SLICC are converted to M5 SimObjects in the following patch, so this patch alone does not compile. Conversion of Garnet network models is also handled in a separate patch; that code is temporarily disabled from compiling to allow testing of interim code.
151 lines
4.8 KiB
C++
151 lines
4.8 KiB
C++
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id: Sequencer.hh 1.70 2006/09/27 14:56:41-05:00 bobba@s1-01.cs.wisc.edu $
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*
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* Description:
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*
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*/
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#ifndef SEQUENCER_H
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#define SEQUENCER_H
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#include "mem/ruby/common/Global.hh"
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#include "mem/ruby/common/Consumer.hh"
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#include "mem/protocol/CacheRequestType.hh"
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#include "mem/protocol/AccessModeType.hh"
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#include "mem/protocol/GenericMachineType.hh"
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#include "mem/protocol/PrefetchBit.hh"
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#include "mem/ruby/system/RubyPort.hh"
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#include "mem/gems_common/Map.hh"
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#include "mem/ruby/common/Address.hh"
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class DataBlock;
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class CacheMsg;
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class MachineID;
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class CacheMemory;
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class RubySequencerParams;
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struct SequencerRequest {
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RubyRequest ruby_request;
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int64_t id;
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Time issue_time;
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SequencerRequest(const RubyRequest & _ruby_request, int64_t _id, Time _issue_time)
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: ruby_request(_ruby_request), id(_id), issue_time(_issue_time)
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{}
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};
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std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
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class Sequencer : public RubyPort, public Consumer {
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public:
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typedef RubySequencerParams Params;
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// Constructors
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Sequencer(const Params *);
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// Destructor
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~Sequencer();
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// Public Methods
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void wakeup(); // Used only for deadlock detection
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void printConfig(ostream& out) const;
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void printProgress(ostream& out) const;
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void writeCallback(const Address& address, DataBlock& data);
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void readCallback(const Address& address, DataBlock& data);
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// called by Tester or Simics
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int64_t makeRequest(const RubyRequest & request);
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int isReady(const RubyRequest& request);
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bool empty() const;
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void print(ostream& out) const;
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void printStats(ostream & out) const;
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void checkCoherence(const Address& address);
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// bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
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// bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
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void removeRequest(SequencerRequest* request);
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private:
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// Private Methods
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bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
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void issueRequest(const RubyRequest& request);
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void hitCallback(SequencerRequest* request, DataBlock& data);
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bool insertRequest(SequencerRequest* request);
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// Private copy constructor and assignment operator
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Sequencer(const Sequencer& obj);
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Sequencer& operator=(const Sequencer& obj);
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private:
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int m_max_outstanding_requests;
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int m_deadlock_threshold;
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CacheMemory* m_dataCache_ptr;
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CacheMemory* m_instCache_ptr;
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// indicates what processor on the chip this sequencer is associated with
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int m_controller_type;
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Map<Address, SequencerRequest*> m_writeRequestTable;
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Map<Address, SequencerRequest*> m_readRequestTable;
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// Global outstanding request count, across all request tables
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int m_outstanding_count;
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bool m_deadlock_check_scheduled;
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int m_store_waiting_on_load_cycles;
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int m_store_waiting_on_store_cycles;
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int m_load_waiting_on_store_cycles;
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int m_load_waiting_on_load_cycles;
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};
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// Output operator declaration
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ostream& operator<<(ostream& out, const Sequencer& obj);
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// ******************* Definitions *******************
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// Output operator definition
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extern inline
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ostream& operator<<(ostream& out, const Sequencer& obj)
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{
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obj.print(out);
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out << flush;
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return out;
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}
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#endif //SEQUENCER_H
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