213 lines
7.8 KiB
Python
213 lines
7.8 KiB
Python
# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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from Pci import PciDevice
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class EtherObject(SimObject):
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type = 'EtherObject'
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abstract = True
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class EtherLink(EtherObject):
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type = 'EtherLink'
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int0 = Port("interface 0")
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int1 = Port("interface 1")
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delay = Param.Latency('0us', "packet transmit delay")
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delay_var = Param.Latency('0ns', "packet transmit delay variability")
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speed = Param.NetworkBandwidth('1Gbps', "link speed")
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dump = Param.EtherDump(NULL, "dump object")
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class EtherBus(EtherObject):
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type = 'EtherBus'
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loopback = Param.Bool(True, "send packet back to the sending interface")
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dump = Param.EtherDump(NULL, "dump object")
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speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
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class EtherTap(EtherObject):
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type = 'EtherTap'
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bufsz = Param.Int(10000, "tap buffer size")
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dump = Param.EtherDump(NULL, "dump object")
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port = Param.UInt16(3500, "tap port")
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class EtherDump(SimObject):
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type = 'EtherDump'
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file = Param.String("dump file")
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maxlen = Param.Int(96, "max portion of packet data to dump")
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class EtherDevice(PciDevice):
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type = 'EtherDevice'
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abstract = True
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interface = Port("Ethernet Interface")
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class IGbE(EtherDevice):
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# Base class for two IGbE adapters listed above
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type = 'IGbE'
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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use_flow_control = Param.Bool(False,
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"Should we use xon/xoff flow contorl (UNIMPLEMENTD)")
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rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
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tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
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rx_desc_cache_size = Param.Int(64,
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"Number of enteries in the rx descriptor cache")
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tx_desc_cache_size = Param.Int(64,
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"Number of enteries in the rx descriptor cache")
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clock = Param.Clock('500MHz', "Clock speed of the device")
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VendorID = 0x8086
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SubsystemID = 0x1008
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SubsystemVendorID = 0x8086
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Status = 0x0000
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BAR0 = 0x00000000
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BAR1 = 0x00000000
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BAR2 = 0x00000000
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BAR3 = 0x00000000
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BAR4 = 0x00000000
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BAR5 = 0x00000000
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MaximumLatency = 0x00
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MinimumGrant = 0xff
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InterruptLine = 0x1e
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InterruptPin = 0x01
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BAR0Size = '128kB'
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wb_delay = Param.Latency('10ns', "delay before desc writeback occurs")
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fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs")
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fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs")
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wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
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tx_read_delay = Param.Latency('0ns', "delay after tx dma read")
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rx_write_delay = Param.Latency('0ns', "delay after rx dma read")
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phy_pid = Param.UInt16("Phy PID that corresponds to device ID")
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phy_epid = Param.UInt16("Phy EPID that corresponds to device ID")
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class IGbE_e1000(IGbE):
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# Older Intel 8254x based gigabit ethernet adapter
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# Uses Intel e1000 driver
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DeviceID = 0x1075
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phy_pid = 0x02A8
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phy_epid = 0x0380
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class IGbE_igb(IGbE):
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# Newer Intel 8257x based gigabit ethernet adapter
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# Uses Intel igb driver and in theory supports packet splitting and LRO
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DeviceID = 0x10C9
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phy_pid = 0x0141
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phy_epid = 0x0CC0
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class EtherDevBase(EtherDevice):
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type = 'EtherDevBase'
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abstract = True
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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clock = Param.Clock('0ns', "State machine processor frequency")
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dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
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dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
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dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
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dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
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rx_delay = Param.Latency('1us', "Receive Delay")
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tx_delay = Param.Latency('1us', "Transmit Delay")
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rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
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tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
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rx_filter = Param.Bool(True, "Enable Receive Filter")
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intr_delay = Param.Latency('10us', "Interrupt propagation delay")
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rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
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tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
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rss = Param.Bool(False, "Receive Side Scaling")
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class NSGigE(EtherDevBase):
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type = 'NSGigE'
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dma_data_free = Param.Bool(False, "DMA of Data is free")
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dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
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dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
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VendorID = 0x100B
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DeviceID = 0x0022
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Status = 0x0290
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BAR0 = 0x00000001
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BAR1 = 0x00000000
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BAR2 = 0x00000000
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BAR3 = 0x00000000
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BAR4 = 0x00000000
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BAR5 = 0x00000000
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MaximumLatency = 0x34
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MinimumGrant = 0xb0
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InterruptLine = 0x1e
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InterruptPin = 0x01
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BAR0Size = '256B'
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BAR1Size = '4kB'
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class Sinic(EtherDevBase):
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type = 'Sinic'
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cxx_class = 'Sinic::Device'
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rx_max_copy = Param.MemorySize('1514B', "rx max copy")
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tx_max_copy = Param.MemorySize('16kB', "tx max copy")
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rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
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rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
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rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
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tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
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tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
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virtual_count = Param.UInt32(1, "Virtualized SINIC")
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zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
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zero_copy_threshold = Param.UInt32(256,
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"Only zero copy above this threshold")
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zero_copy = Param.Bool(False, "Zero copy receive")
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delay_copy = Param.Bool(False, "Delayed copy transmit")
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virtual_addr = Param.Bool(False, "Virtual addressing")
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VendorID = 0x1291
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DeviceID = 0x1293
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Status = 0x0290
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BAR0 = 0x00000000
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BAR1 = 0x00000000
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BAR2 = 0x00000000
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BAR3 = 0x00000000
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BAR4 = 0x00000000
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BAR5 = 0x00000000
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MaximumLatency = 0x34
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MinimumGrant = 0xb0
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InterruptLine = 0x1e
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InterruptPin = 0x01
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BAR0Size = '64kB'
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