Add a regression tester to McPAT. Joel Hestness wrote these tests and Yasuko Eckert modified them to reflect the new McPAT interface and other changes the previous patch made.
401 lines
18 KiB
XML
401 lines
18 KiB
XML
<?xml version="1.0" ?>
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<component id="root" name="root">
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<component id="system" name="system" type="System">
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<param name="core_tech_node" value="40"/>
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<param name="target_core_clockrate" value="1700"/>
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<param name="temperature" value="380"/>
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<param name="interconnect_projection_type" value="1"/>
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<param name="device_type" value="0"/>
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<param name="longer_channel_device" value="0"/>
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<param name="machine_bits" value="64"/>
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<param name="virtual_address_width" value="64"/>
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<param name="physical_address_width" value="36"/>
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<param name="virtual_memory_page_size" value="4096"/>
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<param name="wire_is_mat_type" value="2"/>
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<param name="wire_os_mat_type" value="2"/>
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<param name="delay_wt" value="100"/>
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<param name="area_wt" value="0"/>
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<param name="dynamic_power_wt" value="100"/>
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<param name="leakage_power_wt" value="0"/>
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<param name="cycle_time_wt" value="0"/>
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<param name="delay_dev" value="10000"/>
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<param name="area_dev" value="10000"/>
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<param name="dynamic_power_dev" value="10000"/>
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<param name="leakage_power_dev" value="10000"/>
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<param name="cycle_time_dev" value="10000"/>
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<param name="ed" value="2"/>
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<param name="burst_len" value="1"/>
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<param name="int_prefetch_w" value="1"/>
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<param name="page_sz_bits" value="0"/>
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<param name="rpters_in_htree" value="1"/>
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<param name="ver_htree_wires_over_array" value="0"/>
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<param name="nuca" value="0"/>
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<param name="nuca_bank_count" value="0"/>
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<param name="force_cache_config" value="0"/>
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<param name="wt" value="0"/>
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<param name="force_wiretype" value="0"/>
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<param name="print_detail" value="1"/>
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<param name="add_ecc_b_" value="1"/>
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<stat name="total_cycles" value="150"/>
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<component id="system.core0" name="core0" type="Core">
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<param name="clock_rate" value="1700"/>
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<param name="opt_local" value="0"/>
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<param name="instruction_length" value="32"/>
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<param name="opcode_width" value="8"/>
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<param name="x86" value="1"/>
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<param name="micro_opcode_width" value="8"/>
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<param name="machine_type" value="0"/>
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<param name="number_hardware_threads" value="2"/>
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<param name="fetch_width" value="1"/>
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<param name="number_instruction_fetch_ports" value="1"/>
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<param name="decode_width" value="2"/>
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<param name="issue_width" value="2"/>
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<param name="peak_issue_width" value="2"/>
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<param name="commit_width" value="2"/>
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<param name="fp_issue_width" value="2"/>
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<param name="prediction_width" value="1"/>
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<param name="int_pipelines" value="2"/>
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<param name="fp_pipelines" value="1"/>
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<param name="int_pipeline_depth" value="12"/>
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<param name="fp_pipeline_depth" value="13"/>
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<param name="ALU_per_core" value="2"/>
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<param name="MUL_per_core" value="1"/>
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<param name="FPU_per_core" value="1"/>
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<param name="instruction_buffer_size" value="16"/>
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<param name="instruction_window_scheme" value="0"/>
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<param name="instruction_window_size" value="7"/>
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<param name="fp_instruction_window_size" value="18"/>
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<param name="ROB_size" value="56"/>
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<param name="archi_Regs_IRF_size" value="30"/>
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<param name="archi_Regs_FRF_size" value="48"/>
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<param name="phy_Regs_IRF_size" value="34"/>
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<param name="phy_Regs_FRF_size" value="40"/>
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<param name="rename_scheme" value="0"/>
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<param name="register_window_size" value="0"/>
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<param name="store_buffer_size" value="32"/>
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<param name="load_buffer_size" value="22"/>
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<param name="memory_ports" value="1"/>
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<param name="RAS_size" value="16"/>
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<param name="execu_wire_mat_type" value="2"/>
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<param name="execu_bypass_base_width" value="1"/>
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<param name="execu_bypass_base_height" value="1"/>
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<param name="execu_bypass_start_wiring_level"value="3"/>
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<param name="execu_bypass_route_over_perc" value="1"/>
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<param name="globalCheckpoint" value="32"/>
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<param name="perThreadState" value="8"/>
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<param name="ROB_assoc" value="1"/>
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<param name="ROB_nbanks" value="1"/>
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<param name="ROB_tag_width" value="0"/>
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<param name="scheduler_assoc" value="0"/>
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<param name="scheduler_nbanks" value="1"/>
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<param name="register_window_assoc" value="1"/>
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<param name="register_window_nbanks" value="1"/>
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<param name="register_window_tag_width" value="0"/>
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<param name="register_window_rw_ports" value="1"/>
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<param name="phy_Regs_IRF_assoc" value="1"/>
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<param name="phy_Regs_IRF_nbanks" value="1"/>
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<param name="phy_Regs_IRF_tag_width" value="0"/>
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<param name="phy_Regs_IRF_rd_ports" value="1"/>
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<param name="phy_Regs_IRF_wr_ports" value="1"/>
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<param name="phy_Regs_FRF_assoc" value="1"/>
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<param name="phy_Regs_FRF_nbanks" value="1"/>
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<param name="phy_Regs_FRF_tag_width" value="0"/>
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<param name="phy_Regs_FRF_rd_ports" value="1"/>
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<param name="phy_Regs_FRF_wr_ports" value="1"/>
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<param name="front_rat_nbanks" value="1"/>
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<param name="front_rat_rw_ports" value="1"/>
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<param name="retire_rat_nbanks" value="1"/>
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<param name="retire_rat_rw_ports" value="0"/>
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<param name="freelist_nbanks" value="1"/>
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<param name="freelist_rw_ports" value="1"/>
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<param name="load_buffer_assoc" value="0"/>
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<param name="load_buffer_nbanks" value="1"/>
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<param name="store_buffer_assoc" value="0"/>
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<param name="store_buffer_nbanks" value="1"/>
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<param name="instruction_buffer_assoc" value="1"/>
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<param name="instruction_buffer_nbanks" value="1"/>
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<param name="instruction_buffer_tag_width" value="0"/>
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<stat name="total_instructions" value="100"/>
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<stat name="int_instructions" value="50"/>
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<stat name="fp_instructions" value="50"/>
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<stat name="branch_instructions" value="20"/>
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<stat name="branch_mispredictions" value="2"/>
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<stat name="load_instructions" value="50"/>
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<stat name="store_instructions" value="15"/>
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<stat name="committed_instructions" value="100"/>
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<stat name="committed_int_instructions" value="50"/>
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<stat name="committed_fp_instructions" value="50"/>
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<stat name="pipeline_duty_cycle" value="1"/>
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<stat name="total_cycles" value="150"/>
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<stat name="idle_cycles" value="30"/>
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<stat name="busy_cycles" value="120"/>
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<stat name="ROB_reads" value="100"/>
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<stat name="ROB_writes" value="100"/>
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<stat name="rename_reads" value="100"/>
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<stat name="rename_writes" value="50"/>
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<stat name="fp_rename_reads" value="100"/>
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<stat name="fp_rename_writes" value="50"/>
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<stat name="inst_window_reads" value="50"/>
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<stat name="inst_window_writes" value="50"/>
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<stat name="inst_window_wakeup_accesses" value="50"/>
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<stat name="fp_inst_window_reads" value="50"/>
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<stat name="fp_inst_window_writes" value="50"/>
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<stat name="fp_inst_window_wakeup_accesses" value="50"/>
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<stat name="int_regfile_reads" value="100"/>
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<stat name="float_regfile_reads" value="100"/>
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<stat name="int_regfile_writes" value="50"/>
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<stat name="float_regfile_writes" value="50"/>
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<stat name="function_calls" value="5"/>
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<stat name="context_switches" value="0"/>
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<stat name="ialu_accesses" value="15"/>
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<stat name="fpu_accesses" value="15"/>
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<stat name="mul_accesses" value="15"/>
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<stat name="cdb_alu_accesses" value="15"/>
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<stat name="cdb_mul_accesses" value="15"/>
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<stat name="cdb_fpu_accesses" value="15"/>
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<stat name="IFU_duty_cycle" value="1"/>
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<stat name="LSU_duty_cycle" value="1"/>
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<stat name="MemManU_I_duty_cycle" value="1"/>
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<stat name="MemManU_D_duty_cycle" value="1"/>
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<stat name="ALU_duty_cycle" value="1"/>
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<stat name="MUL_duty_cycle" value="1"/>
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<stat name="FPU_duty_cycle" value="1"/>
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<stat name="ALU_cdb_duty_cycle" value="1"/>
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<stat name="MUL_cdb_duty_cycle" value="1"/>
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<stat name="FPU_cdb_duty_cycle" value="1"/>
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<component id="system.core0.predictor" name="PBT" type="BranchPredictor">
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<param name="assoc" value="1"/>
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<param name="nbanks" value="1"/>
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<param name="local_l1_predictor_size" value="12"/>
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<param name="local_l2_predictor_size" value="4"/>
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<param name="local_predictor_entries" value="8192"/>
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<param name="global_predictor_entries" value="8192"/>
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<param name="global_predictor_bits" value="4"/>
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<param name="chooser_predictor_entries" value="8192"/>
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<param name="chooser_predictor_bits" value="4"/>
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</component>
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<component id="system.core0.itlb" name="itlb" type="InstructionTLB">
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<param name="number_entries" value="512"/>
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<param name="latency" value="8"/>
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<param name="throughput" value="3"/>
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<param name="assoc" value="0"/>
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<param name="nbanks" value="1"/>
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<stat name="total_accesses" value="50"/>
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<stat name="total_misses" value="10"/>
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<stat name="conflicts" value="10"/>
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</component>
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<component id="system.core0.icache" name="Instruction Cache" type="CacheUnit">
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<param name="level" value="1"/>
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<param name="size" value="32768"/>
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<param name="block_size" value="64"/>
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<param name="assoc" value="2"/>
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<param name="num_banks" value="1"/>
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<param name="latency" value="8"/>
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<param name="throughput" value="3"/>
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<param name="miss_buffer_size" value="2"/>
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<param name="fetch_buffer_size" value="2"/>
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<param name="prefetch_buffer_size" value="2"/>
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<param name="writeback_buffer_size" value="0"/>
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<param name="clockrate" value="0"/>
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<param name="tech_type" value="0"/>
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<param name="Directory_type" value="2"/>
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<param name="core_type" value="1"/>
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<param name="wire_mat_type" value="2"/>
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<param name="wire_type" value="0"/>
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<param name="miss_buffer_assoc" value="0"/>
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<param name="fetch_buffer_assoc" value="0"/>
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<param name="prefetch_buffer_assoc" value="0"/>
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<param name="writeback_buffer_assoc" value="0"/>
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<param name="miss_buffer_banks" value="1"/>
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<param name="fetch_buffer_banks" value="1"/>
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<param name="prefetch_buffer_banks" value="1"/>
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<param name="writeback_buffer_banks" value="1"/>
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<param name="cache_access_mode" value="0"/>
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<param name="miss_buff_access_mode" value="2"/>
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<param name="fetch_buff_access_mode" value="2"/>
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<param name="prefetch_buff_access_mode" value="2"/>
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<param name="writeback_buff_access_mode"value="2"/>
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<param name="cache_rw_ports" value="1"/>
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<param name="cache_rd_ports" value="0"/>
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<param name="cache_wr_ports" value="0"/>
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<param name="cache_se_rd_ports" value="0"/>
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<param name="cache_search_ports" value="0"/>
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<param name="miss_buff_rw_ports" value="1"/>
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<param name="miss_buff_rd_ports" value="0"/>
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<param name="miss_buff_wr_ports" value="0"/>
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<param name="miss_buff_se_rd_ports" value="0"/>
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<param name="miss_buff_search_ports" value="1"/>
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<param name="fetch_buff_rw_ports" value="1"/>
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<param name="fetch_buff_rd_ports" value="0"/>
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<param name="fetch_buff_wr_ports" value="0"/>
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<param name="fetch_buff_se_rd_ports" value="0"/>
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<param name="fetch_buff_search_ports" value="1"/>
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<param name="pf_buff_rw_ports" value="1"/>
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<param name="pf_buff_rd_ports" value="0"/>
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<param name="pf_buff_wr_ports" value="0"/>
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<param name="pf_buff_se_rd_ports" value="0"/>
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<param name="pf_buff_search_ports" value="1"/>
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<param name="wb_buff_rw_ports" value="1"/>
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<param name="wb_buff_rd_ports" value="0"/>
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<param name="wb_buff_wr_ports" value="0"/>
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<param name="wb_buff_se_rd_ports" value="0"/>
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<param name="wb_buff_search_ports" value="1"/>
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<param name="pure_ram" value="0"/>
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<stat name="read_accesses" value="50"/>
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<stat name="read_misses" value="12"/>
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<stat name="conflicts" value="1"/>
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<stat name="duty_cycle" value="1"/>
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</component>
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<component id="system.core0.dtlb" name="dtlb" type="DataTLB">
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<param name="number_entries" value="512"/>
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<param name="latency" value="8"/>
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<param name="throughput" value="3"/>
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<param name="assoc" value="0"/>
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<param name="nbanks" value="1"/>
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<stat name="read_accesses" value="65"/>
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<stat name="read_misses" value="40"/>
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<stat name="conflicts" value="40"/>
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</component>
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<component id="system.core0.dcache" name="Data Cache" type="CacheUnit">
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<param name="level" value="1"/>
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<param name="size" value="32768"/>
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<param name="block_size" value="64"/>
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<param name="assoc" value="8"/>
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<param name="num_banks" value="1"/>
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<param name="latency" value="8"/>
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<param name="throughput" value="3"/>
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<param name="miss_buffer_size" value="8"/>
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<param name="fetch_buffer_size" value="8"/>
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<param name="prefetch_buffer_size" value="8"/>
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<param name="writeback_buffer_size" value="8"/>
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<param name="clockrate" value="0"/>
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<param name="tech_type" value="0"/>
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<param name="Directory_type" value="2"/>
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<param name="core_type" value="1"/>
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<param name="wire_mat_type" value="2"/>
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<param name="wire_type" value="0"/>
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<param name="miss_buffer_assoc" value="0"/>
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<param name="fetch_buffer_assoc" value="0"/>
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<param name="prefetch_buffer_assoc" value="0"/>
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<param name="writeback_buffer_assoc" value="0"/>
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<param name="miss_buffer_banks" value="1"/>
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<param name="fetch_buffer_banks" value="1"/>
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<param name="prefetch_buffer_banks" value="1"/>
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<param name="writeback_buffer_banks" value="1"/>
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<param name="cache_access_mode" value="0"/>
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<param name="miss_buff_access_mode" value="2"/>
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<param name="fetch_buff_access_mode" value="2"/>
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<param name="prefetch_buff_access_mode" value="2"/>
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<param name="writeback_buff_access_mode"value="2"/>
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<param name="cache_rw_ports" value="1"/>
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<param name="cache_rd_ports" value="0"/>
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<param name="cache_wr_ports" value="0"/>
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<param name="cache_se_rd_ports" value="0"/>
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<param name="cache_search_ports" value="0"/>
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<param name="miss_buff_rw_ports" value="1"/>
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<param name="miss_buff_rd_ports" value="0"/>
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<param name="miss_buff_wr_ports" value="0"/>
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<param name="miss_buff_se_rd_ports" value="0"/>
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<param name="miss_buff_search_ports" value="1"/>
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<param name="fetch_buff_rw_ports" value="1"/>
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<param name="fetch_buff_rd_ports" value="0"/>
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<param name="fetch_buff_wr_ports" value="0"/>
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<param name="fetch_buff_se_rd_ports" value="0"/>
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<param name="fetch_buff_search_ports" value="1"/>
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<param name="pf_buff_rw_ports" value="1"/>
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<param name="pf_buff_rd_ports" value="0"/>
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<param name="pf_buff_wr_ports" value="0"/>
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<param name="pf_buff_se_rd_ports" value="0"/>
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<param name="pf_buff_search_ports" value="1"/>
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<param name="wb_buff_rw_ports" value="1"/>
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<param name="wb_buff_rd_ports" value="0"/>
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<param name="wb_buff_wr_ports" value="0"/>
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<param name="wb_buff_se_rd_ports" value="0"/>
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<param name="wb_buff_search_ports" value="1"/>
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<param name="pure_ram" value="0"/>
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<stat name="read_accesses" value="50"/>
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<stat name="write_accesses" value="15"/>
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<stat name="read_misses" value="12"/>
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<stat name="write_misses" value="3"/>
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<stat name="conflicts" value="1"/>
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<stat name="duty_cycle" value="1"/>
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</component>
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<component id="system.core0.btargetbuf" name="btargetbuf" type="BranchTargetBuffer">
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<param name="size" value="8192"/>
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<param name="block_size" value="4"/>
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<param name="assoc" value="2"/>
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<param name="num_banks" value="1"/>
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<param name="latency" value="1"/>
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<param name="throughput" value="3"/>
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<param name="rw_ports" value="1"/>
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<stat name="read_accesses" value="20"/>
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<stat name="write_accesses" value="20"/>
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</component>
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</component>
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<component id="system.L20" name="L2 Cache" type="CacheUnit">
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<param name="level" value="2"/>
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<param name="size" value="524288"/>
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<param name="block_size" value="64"/>
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<param name="assoc" value="16"/>
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<param name="num_banks" value="1"/>
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<param name="latency" value="8"/>
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<param name="throughput" value="23"/>
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<param name="miss_buffer_size" value="16"/>
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<param name="fetch_buffer_size" value="16"/>
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<param name="prefetch_buffer_size" value="16"/>
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<param name="writeback_buffer_size" value="16"/>
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<param name="clockrate" value="1700"/>
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<param name="device_type" value="0"/>
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<param name="tech_type" value="0"/>
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<param name="Directory_type" value="2"/>
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<param name="core_type" value="1"/>
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<param name="wire_mat_type" value="2"/>
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<param name="wire_type" value="0"/>
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<param name="miss_buffer_assoc" value="0"/>
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<param name="fetch_buffer_assoc" value="0"/>
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<param name="prefetch_buffer_assoc" value="0"/>
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<param name="writeback_buffer_assoc" value="0"/>
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<param name="miss_buffer_banks" value="1"/>
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<param name="fetch_buffer_banks" value="1"/>
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<param name="prefetch_buffer_banks" value="1"/>
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<param name="writeback_buffer_banks" value="1"/>
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<param name="cache_access_mode" value="1"/>
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<param name="miss_buff_access_mode" value="0"/>
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<param name="fetch_buff_access_mode" value="0"/>
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<param name="prefetch_buff_access_mode" value="0"/>
|
|
<param name="writeback_buff_access_mode"value="0"/>
|
|
<param name="cache_rw_ports" value="1"/>
|
|
<param name="cache_rd_ports" value="0"/>
|
|
<param name="cache_wr_ports" value="0"/>
|
|
<param name="cache_se_rd_ports" value="0"/>
|
|
<param name="cache_search_ports" value="0"/>
|
|
<param name="miss_buff_rw_ports" value="1"/>
|
|
<param name="miss_buff_rd_ports" value="0"/>
|
|
<param name="miss_buff_wr_ports" value="0"/>
|
|
<param name="miss_buff_se_rd_ports" value="0"/>
|
|
<param name="miss_buff_search_ports" value="1"/>
|
|
<param name="fetch_buff_rw_ports" value="1"/>
|
|
<param name="fetch_buff_rd_ports" value="0"/>
|
|
<param name="fetch_buff_wr_ports" value="0"/>
|
|
<param name="fetch_buff_se_rd_ports" value="0"/>
|
|
<param name="fetch_buff_search_ports" value="1"/>
|
|
<param name="pf_buff_rw_ports" value="1"/>
|
|
<param name="pf_buff_rd_ports" value="0"/>
|
|
<param name="pf_buff_wr_ports" value="0"/>
|
|
<param name="pf_buff_se_rd_ports" value="0"/>
|
|
<param name="pf_buff_search_ports" value="1"/>
|
|
<param name="wb_buff_rw_ports" value="1"/>
|
|
<param name="wb_buff_rd_ports" value="0"/>
|
|
<param name="wb_buff_wr_ports" value="0"/>
|
|
<param name="wb_buff_se_rd_ports" value="0"/>
|
|
<param name="wb_buff_search_ports" value="1"/>
|
|
<param name="pure_ram" value="0"/>
|
|
<stat name="read_accesses" value="52"/>
|
|
<stat name="write_accesses" value="3"/>
|
|
<stat name="read_misses" value="35"/>
|
|
<stat name="write_misses" value="3"/>
|
|
<stat name="conflicts" value="38"/>
|
|
<stat name="duty_cycle" value="1.0"/>
|
|
</component>
|
|
</component>
|
|
</component>
|