Add a regression tester to McPAT. Joel Hestness wrote these tests and Yasuko Eckert modified them to reflect the new McPAT interface and other changes the previous patch made.
242 lines
11 KiB
XML
242 lines
11 KiB
XML
<?xml version="1.0" ?>
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<component id="root" name="root">
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<component id="system" name="system" type="System">
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<param name="core_tech_node" value="40"/>
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<param name="target_core_clockrate" value="1400"/>
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<param name="temperature" value="360"/>
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<param name="interconnect_projection_type" value="0"/>
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<param name="device_type" value="0"/>
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<param name="machine_bits" value="64"/>
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<param name="virtual_address_width" value="64"/>
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<param name="physical_address_width" value="52"/>
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<param name="virtual_memory_page_size" value="4096"/>
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<param name="wire_is_mat_type" value="2"/>
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<param name="wire_os_mat_type" value="2"/>
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<param name="delay_wt" value="100"/>
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<param name="area_wt" value="0"/>
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<param name="dynamic_power_wt" value="100"/>
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<param name="leakage_power_wt" value="0"/>
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<param name="cycle_time_wt" value="0"/>
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<param name="delay_dev" value="10000"/>
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<param name="area_dev" value="10000"/>
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<param name="dynamic_power_dev" value="10000"/>
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<param name="leakage_power_dev" value="10000"/>
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<param name="cycle_time_dev" value="10000"/>
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<param name="ed" value="2"/>
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<param name="burst_len" value="1"/>
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<param name="int_prefetch_w" value="1"/>
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<param name="page_sz_bits" value="0"/>
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<param name="rpters_in_htree" value="1"/>
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<param name="ver_htree_wires_over_array" value="0"/>
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<param name="nuca" value="0"/>
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<param name="nuca_bank_count" value="0"/>
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<param name="force_cache_config" value="0"/>
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<param name="wt" value="0"/>
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<param name="force_wiretype" value="0"/>
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<param name="print_detail" value="1"/>
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<param name="add_ecc_b_" value="1"/>
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<stat name="total_cycles" value="566948"/>
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<component id="system.l1_cntrl0" name="l1_cntrl0" type="CacheController">
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<component id="system.l1_cntrl0.L1DcacheMemory" name="L1DcacheMemory" type="CacheUnit">
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<param name="level" value="1"/>
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<param name="size" value="32768"/>
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<param name="block_size" value="64"/>
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<param name="assoc" value="2"/>
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<param name="num_banks" value="1"/>
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<param name="latency" value="2"/>
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<param name="throughput" value="1"/>
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<param name="miss_buffer_size" value="2"/>
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<param name="fetch_buffer_size" value="2"/>
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<param name="prefetch_buffer_size" value="2"/>
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<param name="writeback_buffer_size" value="2"/>
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<param name="clockrate" value="2000"/>
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<param name="device_type" value="0"/>
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<param name="tech_type" value="0"/>
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<param name="Directory_type" value="2"/>
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<param name="core_type" value="1"/>
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<param name="wire_mat_type" value="2"/>
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<param name="wire_type" value="0"/>
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<param name="miss_buffer_assoc" value="0"/>
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<param name="fetch_buffer_assoc" value="0"/>
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<param name="prefetch_buffer_assoc" value="0"/>
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<param name="writeback_buffer_assoc" value="0"/>
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<param name="miss_buffer_banks" value="1"/>
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<param name="fetch_buffer_banks" value="1"/>
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<param name="prefetch_buffer_banks" value="1"/>
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<param name="writeback_buffer_banks" value="1"/>
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<param name="cache_access_mode" value="0"/>
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<param name="miss_buff_access_mode" value="2"/>
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<param name="fetch_buff_access_mode" value="2"/>
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<param name="prefetch_buff_access_mode" value="2"/>
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<param name="writeback_buff_access_mode"value="2"/>
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<param name="cache_rw_ports" value="1"/>
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<param name="cache_rd_ports" value="0"/>
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<param name="cache_wr_ports" value="0"/>
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<param name="cache_se_rd_ports" value="0"/>
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<param name="cache_search_ports" value="0"/>
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<param name="miss_buff_rw_ports" value="1"/>
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<param name="miss_buff_rd_ports" value="0"/>
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<param name="miss_buff_wr_ports" value="0"/>
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<param name="miss_buff_se_rd_ports" value="0"/>
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<param name="miss_buff_search_ports" value="1"/>
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<param name="fetch_buff_rw_ports" value="1"/>
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<param name="fetch_buff_rd_ports" value="0"/>
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<param name="fetch_buff_wr_ports" value="0"/>
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<param name="fetch_buff_se_rd_ports" value="0"/>
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<param name="fetch_buff_search_ports" value="1"/>
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<param name="pf_buff_rw_ports" value="1"/>
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<param name="pf_buff_rd_ports" value="0"/>
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<param name="pf_buff_wr_ports" value="0"/>
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<param name="pf_buff_se_rd_ports" value="0"/>
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<param name="pf_buff_search_ports" value="1"/>
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<param name="wb_buff_rw_ports" value="1"/>
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<param name="wb_buff_rd_ports" value="0"/>
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<param name="wb_buff_wr_ports" value="0"/>
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<param name="wb_buff_se_rd_ports" value="0"/>
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<param name="wb_buff_search_ports" value="1"/>
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<param name="pure_ram" value="0"/>
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<stat name="num_data_array_reads" value="47291"/>
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<stat name="num_data_array_writes" value="51619"/>
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<stat name="num_tag_array_reads" value="91498"/>
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<stat name="num_tag_array_writes" value="17078"/>
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<stat name="read_misses" value="174"/>
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<stat name="write_misses" value="12046"/>
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<stat name="conflicts" value="12120"/>
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<stat name="duty_cycle" value="1"/>
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</component>
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<component id="system.l1_cntrl0.L1IcacheMemory" name="L1IcacheMemory" type="CacheUnit">
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<param name="level" value="1"/>
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<param name="size" value="32768"/>
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<param name="block_size" value="64"/>
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<param name="assoc" value="2"/>
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<param name="num_banks" value="1"/>
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<param name="latency" value="2"/>
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<param name="throughput" value="1"/>
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<param name="miss_buffer_size" value="2"/>
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<param name="fetch_buffer_size" value="2"/>
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<param name="prefetch_buffer_size" value="2"/>
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<param name="writeback_buffer_size" value="2"/>
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<param name="clockrate" value="2000"/>
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<param name="device_type" value="0"/>
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<param name="tech_type" value="0"/>
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<param name="Directory_type" value="2"/>
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<param name="core_type" value="1"/>
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<param name="wire_mat_type" value="2"/>
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<param name="wire_type" value="0"/>
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<param name="miss_buffer_assoc" value="0"/>
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<param name="fetch_buffer_assoc" value="0"/>
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<param name="prefetch_buffer_assoc" value="0"/>
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<param name="writeback_buffer_assoc" value="0"/>
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<param name="miss_buffer_banks" value="1"/>
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<param name="fetch_buffer_banks" value="1"/>
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<param name="prefetch_buffer_banks" value="1"/>
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<param name="writeback_buffer_banks" value="1"/>
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<param name="cache_access_mode" value="0"/>
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<param name="miss_buff_access_mode" value="2"/>
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<param name="fetch_buff_access_mode" value="2"/>
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<param name="prefetch_buff_access_mode" value="2"/>
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<param name="writeback_buff_access_mode"value="2"/>
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<param name="cache_rw_ports" value="1"/>
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<param name="cache_rd_ports" value="0"/>
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<param name="cache_wr_ports" value="0"/>
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<param name="cache_se_rd_ports" value="0"/>
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<param name="cache_search_ports" value="0"/>
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<param name="miss_buff_rw_ports" value="1"/>
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<param name="miss_buff_rd_ports" value="0"/>
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<param name="miss_buff_wr_ports" value="0"/>
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<param name="miss_buff_se_rd_ports" value="0"/>
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<param name="miss_buff_search_ports" value="1"/>
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<param name="fetch_buff_rw_ports" value="1"/>
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<param name="fetch_buff_rd_ports" value="0"/>
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<param name="fetch_buff_wr_ports" value="0"/>
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<param name="fetch_buff_se_rd_ports" value="0"/>
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<param name="fetch_buff_search_ports" value="1"/>
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<param name="pf_buff_rw_ports" value="1"/>
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<param name="pf_buff_rd_ports" value="0"/>
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<param name="pf_buff_wr_ports" value="0"/>
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<param name="pf_buff_se_rd_ports" value="0"/>
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<param name="pf_buff_search_ports" value="1"/>
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<param name="wb_buff_rw_ports" value="1"/>
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<param name="wb_buff_rd_ports" value="0"/>
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<param name="wb_buff_wr_ports" value="0"/>
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<param name="wb_buff_se_rd_ports" value="0"/>
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<param name="wb_buff_search_ports" value="1"/>
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<param name="pure_ram" value="0"/>
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<stat name="num_data_array_reads" value="253831"/>
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<stat name="num_data_array_writes" value="3497"/>
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<stat name="num_tag_array_reads" value="253291"/>
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<stat name="num_tag_array_writes" value="10845"/>
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<stat name="read_misses" value="100"/>
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<stat name="conflicts" value="99"/>
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<stat name="duty_cycle" value="1"/>
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</component>
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<component id="system.l1_cntrl0.L2cacheMemory" name="L2cacheMemory" type="CacheUnit">
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<param name="level" value="2"/>
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<param name="size" value="2097152"/>
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<param name="block_size" value="64"/>
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<param name="assoc" value="16"/>
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<param name="num_banks" value="1"/>
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<param name="latency" value="10"/>
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<param name="throughput" value="1"/>
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<param name="miss_buffer_size" value="2"/>
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<param name="fetch_buffer_size" value="2"/>
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<param name="prefetch_buffer_size" value="2"/>
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<param name="writeback_buffer_size" value="2"/>
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<param name="clockrate" value="2000"/>
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<param name="device_type" value="0"/>
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<param name="tech_type" value="0"/>
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<param name="Directory_type" value="2"/>
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<param name="core_type" value="1"/>
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<param name="wire_mat_type" value="2"/>
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<param name="wire_type" value="0"/>
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<param name="miss_buffer_assoc" value="0"/>
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<param name="fetch_buffer_assoc" value="0"/>
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<param name="prefetch_buffer_assoc" value="0"/>
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<param name="writeback_buffer_assoc" value="0"/>
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<param name="miss_buffer_banks" value="1"/>
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<param name="fetch_buffer_banks" value="1"/>
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<param name="prefetch_buffer_banks" value="1"/>
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<param name="writeback_buffer_banks" value="1"/>
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<param name="cache_access_mode" value="1"/>
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<param name="miss_buff_access_mode" value="0"/>
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<param name="fetch_buff_access_mode" value="0"/>
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<param name="prefetch_buff_access_mode" value="0"/>
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<param name="writeback_buff_access_mode"value="0"/>
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<param name="cache_rw_ports" value="1"/>
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<param name="cache_rd_ports" value="0"/>
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<param name="cache_wr_ports" value="0"/>
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<param name="cache_se_rd_ports" value="0"/>
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<param name="cache_search_ports" value="0"/>
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<param name="miss_buff_rw_ports" value="1"/>
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<param name="miss_buff_rd_ports" value="0"/>
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<param name="miss_buff_wr_ports" value="0"/>
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<param name="miss_buff_se_rd_ports" value="0"/>
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<param name="miss_buff_search_ports" value="1"/>
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<param name="fetch_buff_rw_ports" value="1"/>
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<param name="fetch_buff_rd_ports" value="0"/>
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<param name="fetch_buff_wr_ports" value="0"/>
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<param name="fetch_buff_se_rd_ports" value="0"/>
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<param name="fetch_buff_search_ports" value="1"/>
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<param name="pf_buff_rw_ports" value="1"/>
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<param name="pf_buff_rd_ports" value="0"/>
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<param name="pf_buff_wr_ports" value="0"/>
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<param name="pf_buff_se_rd_ports" value="0"/>
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<param name="pf_buff_search_ports" value="1"/>
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<param name="wb_buff_rw_ports" value="1"/>
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<param name="wb_buff_rd_ports" value="0"/>
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<param name="wb_buff_wr_ports" value="0"/>
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<param name="wb_buff_se_rd_ports" value="0"/>
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<param name="wb_buff_search_ports" value="1"/>
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<param name="pure_ram" value="0"/>
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<stat name="num_data_array_reads" value="3959"/>
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<stat name="num_data_array_writes" value="8086"/>
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<stat name="num_tag_array_reads" value="274"/>
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<stat name="num_tag_array_writes" value="12046"/>
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<stat name="read_misses" value="27"/>
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<stat name="write_misses" value="1204"/>
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<stat name="conflicts" value="1231"/>
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<stat name="duty_cycle" value="1"/>
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</component>
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</component>
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</component>
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</component>
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