arch/sparc/isa/base.isa: Added a set of abbreviations for the different condition tests. arch/sparc/isa/decoder.isa: Fixes and additions to get syscall emulation closer to working. arch/sparc/isa/formats/branch.isa: Fixed branches so that the immediate version actually uses the immediate value arch/sparc/isa/formats/integerop.isa: Compute the condition codes -before- writing to the state of the machine. arch/sparc/isa/formats/mem.isa: An attempt to fix up the output of the disassembly of loads and stores. arch/sparc/isa/formats/trap.isa: Added code to disassemble a trap instruction. This probably needs to be fixed up so there are immediate and register versions. arch/sparc/isa/operands.isa: Added an R1 operand, and fixed up the numbering arch/sparc/isa_traits.hh: SyscallNumReg is no longer needed, the max number of sources and destinations are fixed up, and the syscall return uses xcc instead of icc. arch/sparc/linux/process.cc: arch/sparc/linux/process.hh: Added a getresuidFunc syscall implementation. This isn't actually used, but I thought it was and will leave it in. arch/sparc/process.cc: arch/sparc/process.hh: Fixed up how the initial stack frame is set up. arch/sparc/regfile.hh: Changed the number of windows from 6 to 32 so we don't have to worry about spill and fill traps for now, and commented out the register file setting itself up. cpu/cpu_exec_context.hh: cpu/exec_context.hh: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Changed the syscall mechanism to pass down the syscall number directly. --HG-- extra : convert_revision : 15723b949a0ddb3d24e68c079343b4dba2439f43
166 lines
4.9 KiB
Text
166 lines
4.9 KiB
Text
////////////////////////////////////////////////////////////////////
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//
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// Mem instructions
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//
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output header {{
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/**
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* Base class for memory operations.
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*/
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class Mem : public SparcStaticInst
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{
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protected:
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// Constructor
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Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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SparcStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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/**
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* Class for memory operations which use an immediate offset.
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*/
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class MemImm : public Mem
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{
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protected:
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// Constructor
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MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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Mem(mnem, _machInst, __opClass), imm(SIMM13)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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int32_t imm;
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};
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}};
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output decoder {{
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std::string Mem::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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bool load = flags[IsLoad];
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bool save = flags[IsStore];
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printMnemonic(response, mnemonic);
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if(save)
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{
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printReg(response, _srcRegIdx[0]);
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ccprintf(response, ", ");
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}
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ccprintf(response, "[ ");
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printReg(response, _srcRegIdx[!save ? 0 : 1]);
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ccprintf(response, " + ");
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printReg(response, _srcRegIdx[!save ? 1 : 2]);
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ccprintf(response, " ]");
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if(load)
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{
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ccprintf(response, ", ");
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printReg(response, _destRegIdx[0]);
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}
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return response.str();
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}
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std::string MemImm::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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bool load = flags[IsLoad];
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bool save = flags[IsStore];
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printMnemonic(response, mnemonic);
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if(save)
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{
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printReg(response, _srcRegIdx[0]);
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ccprintf(response, ", ");
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}
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ccprintf(response, "[ ");
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printReg(response, _srcRegIdx[!save ? 0 : 1]);
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ccprintf(response, " + 0x%x ]", imm);
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if(load)
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{
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ccprintf(response, ", ");
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printReg(response, _destRegIdx[0]);
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}
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return response.str();
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}
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}};
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def template MemExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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%(load)s;
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%(code)s;
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%(store)s;
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if(fault == NoFault)
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{
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//Write the resulting state to the execution context
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%(op_wb)s;
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}
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return fault;
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}
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}};
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let {{
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# Leave memAccessFlags at 0 for now
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loadString = "xc->read(EA, (uint%(width)s_t&)Mem, 0);"
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storeString = "uint64_t write_result = 0; \
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xc->write((uint%(width)s_t)Mem, EA, 0, &write_result);"
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def doMemFormat(code, load, store, name, Name, opt_flags):
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addrCalcReg = 'EA = Rs1 + Rs2;'
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addrCalcImm = 'EA = Rs1 + SIMM13;'
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iop = InstObjParams(name, Name, 'Mem', code,
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opt_flags, ("ea_code", addrCalcReg),
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("load", load), ("store", store))
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iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code,
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opt_flags, ("ea_code", addrCalcImm),
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("load", load), ("store", store))
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header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
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decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
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decode_block = ROrImmDecode.subst(iop)
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exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
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return (header_output, decoder_output, exec_output, decode_block)
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}};
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def format Load(code, width, *opt_flags) {{
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(header_output,
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decoder_output,
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exec_output,
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decode_block) = doMemFormat(code,
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loadString % {"width":width}, '', name, Name, opt_flags)
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}};
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def format Store(code, width, *opt_flags) {{
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(header_output,
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decoder_output,
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exec_output,
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decode_block) = doMemFormat(code, '',
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storeString % {"width":width}, name, Name, opt_flags)
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}};
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def format LoadStore(code, width, *opt_flags) {{
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(header_output,
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decoder_output,
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exec_output,
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decode_block) = doMemFormat(code,
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loadString % {"width":width}, storeString % {"width":width},
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name, Name, opt_flags)
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}};
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