arch/sparc/isa/base.isa: Added a set of abbreviations for the different condition tests. arch/sparc/isa/decoder.isa: Fixes and additions to get syscall emulation closer to working. arch/sparc/isa/formats/branch.isa: Fixed branches so that the immediate version actually uses the immediate value arch/sparc/isa/formats/integerop.isa: Compute the condition codes -before- writing to the state of the machine. arch/sparc/isa/formats/mem.isa: An attempt to fix up the output of the disassembly of loads and stores. arch/sparc/isa/formats/trap.isa: Added code to disassemble a trap instruction. This probably needs to be fixed up so there are immediate and register versions. arch/sparc/isa/operands.isa: Added an R1 operand, and fixed up the numbering arch/sparc/isa_traits.hh: SyscallNumReg is no longer needed, the max number of sources and destinations are fixed up, and the syscall return uses xcc instead of icc. arch/sparc/linux/process.cc: arch/sparc/linux/process.hh: Added a getresuidFunc syscall implementation. This isn't actually used, but I thought it was and will leave it in. arch/sparc/process.cc: arch/sparc/process.hh: Fixed up how the initial stack frame is set up. arch/sparc/regfile.hh: Changed the number of windows from 6 to 32 so we don't have to worry about spill and fill traps for now, and commented out the register file setting itself up. cpu/cpu_exec_context.hh: cpu/exec_context.hh: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Changed the syscall mechanism to pass down the syscall number directly. --HG-- extra : convert_revision : 15723b949a0ddb3d24e68c079343b4dba2439f43
287 lines
8.4 KiB
Text
287 lines
8.4 KiB
Text
////////////////////////////////////////////////////////////////////
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//
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// Branch instructions
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//
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output header {{
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/**
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* Base class for branch operations.
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*/
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class Branch : public SparcStaticInst
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{
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protected:
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// Constructor
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Branch(const char *mnem, MachInst _machInst, OpClass __opClass) :
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SparcStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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/**
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* Base class for branch operations with an immediate displacement.
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*/
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class BranchDisp : public Branch
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{
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protected:
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// Constructor
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BranchDisp(const char *mnem, MachInst _machInst,
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OpClass __opClass) :
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Branch(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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int32_t disp;
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};
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/**
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* Base class for branches with 19 bit displacements.
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*/
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class Branch19 : public BranchDisp
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{
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protected:
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// Constructor
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Branch19(const char *mnem, MachInst _machInst,
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OpClass __opClass) :
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BranchDisp(mnem, _machInst, __opClass)
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{
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disp = sign_ext(DISP19 << 2, 21);
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}
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};
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/**
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* Base class for branches with 22 bit displacements.
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*/
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class Branch22 : public BranchDisp
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{
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protected:
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// Constructor
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Branch22(const char *mnem, MachInst _machInst,
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OpClass __opClass) :
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BranchDisp(mnem, _machInst, __opClass)
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{
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disp = sign_ext(DISP22 << 2, 24);
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}
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};
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/**
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* Base class for branches with 30 bit displacements.
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*/
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class Branch30 : public BranchDisp
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{
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protected:
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// Constructor
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Branch30(const char *mnem, MachInst _machInst,
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OpClass __opClass) :
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BranchDisp(mnem, _machInst, __opClass)
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{
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disp = sign_ext(DISP30 << 2, 32);
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}
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};
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/**
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* Base class for 16bit split displacements.
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*/
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class BranchSplit : public BranchDisp
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{
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protected:
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// Constructor
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BranchSplit(const char *mnem, MachInst _machInst,
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OpClass __opClass) :
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BranchDisp(mnem, _machInst, __opClass)
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{
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disp = sign_ext((D16HI << 16) | (D16LO << 2), 18);
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}
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};
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/**
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* Base class for branches that use an immediate and a register to
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* compute their displacements.
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*/
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class BranchImm13 : public Branch
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{
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protected:
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// Constructor
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BranchImm13(const char *mnem, MachInst _machInst, OpClass __opClass) :
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Branch(mnem, _machInst, __opClass), imm(sign_ext(SIMM13, 13))
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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int32_t imm;
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};
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}};
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output decoder {{
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std::string Branch::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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printMnemonic(response, mnemonic);
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if (_numSrcRegs > 0)
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{
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printReg(response, _srcRegIdx[0]);
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for(int x = 1; x < _numSrcRegs; x++)
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{
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response << ", ";
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printReg(response, _srcRegIdx[x]);
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}
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}
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if (_numDestRegs > 0)
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{
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if(_numSrcRegs > 0)
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response << ", ";
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printReg(response, _destRegIdx[0]);
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}
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return response.str();
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}
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std::string BranchImm13::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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printMnemonic(response, mnemonic);
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if (_numSrcRegs > 0)
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{
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printReg(response, _srcRegIdx[0]);
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for(int x = 1; x < _numSrcRegs; x++)
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{
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response << ", ";
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printReg(response, _srcRegIdx[x]);
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}
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}
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if(_numSrcRegs > 0)
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response << ", ";
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ccprintf(response, "0x%x", imm);
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if (_numDestRegs > 0)
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{
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response << ", ";
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printReg(response, _destRegIdx[0]);
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}
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return response.str();
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}
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std::string BranchDisp::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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std::string symbol;
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Addr symbolAddr;
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Addr target = disp + pc;
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printMnemonic(response, mnemonic);
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ccprintf(response, "0x%x", target);
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if(symtab->findNearestSymbol(target, symbol, symbolAddr))
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{
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ccprintf(response, " <%s", symbol);
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if(symbolAddr != target)
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ccprintf(response, "+0x%x>", target - symbolAddr);
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else
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ccprintf(response, ">");
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}
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return response.str();
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}
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}};
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def template BranchExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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//Attempt to execute the instruction
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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NNPC = xc->readNextNPC();
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%(code)s;
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if(fault == NoFault)
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{
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//Write the resulting state to the execution context
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%(op_wb)s;
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}
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return fault;
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}
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}};
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// Primary format for branch instructions:
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def format Branch(code, *opt_flags) {{
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(usesImm, code, immCode,
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rString, iString) = splitOutImm(code)
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iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = BranchExecute.subst(iop)
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if usesImm:
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imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString,
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immCode, opt_flags)
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header_output += BasicDeclare.subst(imm_iop)
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decoder_output += BasicConstructor.subst(imm_iop)
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exec_output += BranchExecute.subst(imm_iop)
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decode_block = ROrImmDecode.subst(iop)
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else:
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decode_block = BasicDecode.subst(iop)
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}};
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// Primary format for branch instructions:
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def format Branch19(code, *opt_flags) {{
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codeBlk = CodeBlock(code)
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iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = BranchExecute.subst(iop)
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decode_block = BasicDecode.subst(iop)
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}};
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// Primary format for branch instructions:
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def format Branch22(code, *opt_flags) {{
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codeBlk = CodeBlock(code)
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iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = BranchExecute.subst(iop)
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decode_block = BasicDecode.subst(iop)
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}};
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// Primary format for branch instructions:
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def format Branch30(code, *opt_flags) {{
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codeBlk = CodeBlock(code)
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iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = BranchExecute.subst(iop)
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decode_block = BasicDecode.subst(iop)
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}};
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// Primary format for branch instructions:
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def format BranchSplit(code, *opt_flags) {{
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codeBlk = CodeBlock(code)
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iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = BranchExecute.subst(iop)
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decode_block = BasicDecode.subst(iop)
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}};
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