207 lines
23 KiB
Text
207 lines
23 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1459378 # Simulator instruction rate (inst/s)
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host_mem_usage 198104 # Number of bytes of host memory used
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host_seconds 1024.89 # Real time elapsed on the host
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host_tick_rate 1680505604 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1495700470 # Number of instructions simulated
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sim_seconds 1.722332 # Number of seconds simulated
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sim_ticks 1722331568000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 24153.691272 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21153.690114 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 382374810 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 41722410000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1727372 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 36540292000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1727372 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 149160200 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 55999.912307 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912307 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 147694869 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 82058407500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.009824 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1465331 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 77662414500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.009824 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1465331 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 210.745406 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 533262382 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 38769.912986 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 35769.912360 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 530069679 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 123780817500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.005987 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 3192703 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 114202706500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.005987 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 3192703 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 533262382 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 38769.912986 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 35769.912360 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 530069679 # number of overall hits
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system.cpu.dcache.overall_miss_latency 123780817500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.005987 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 3192703 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 114202706500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.005987 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 3192703 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 2514317 # number of replacements
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system.cpu.dcache.sampled_refs 2518413 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4086.814341 # Cycle average of tags in use
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system.cpu.dcache.total_refs 530743969 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 8217895000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 1463113 # number of writebacks
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system.cpu.icache.ReadReq_accesses 1068347073 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 48626.865672 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 45626.865672 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1068344259 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 136836000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 128394000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 379653.254797 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 1068347073 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 48626.865672 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency
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system.cpu.icache.demand_hits 1068344259 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 136836000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
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system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 128394000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 1068347073 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 48626.865672 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 1068344259 # number of overall hits
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system.cpu.icache.overall_miss_latency 136836000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
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system.cpu.icache.overall_misses 2814 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 128394000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 1253 # number of replacements
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system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 887.538461 # Cycle average of tags in use
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system.cpu.icache.total_refs 1068344259 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 791041 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014538 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 41134143500 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 791041 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 31641640000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 791041 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 1730186 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 1310266 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 21835840000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.242702 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 419920 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 16796800000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242702 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 419920 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 674290 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.203458 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 35055800000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 674290 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26971600000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 674290 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 1463113 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 1463113 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 3.423900 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 2521227 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000.009497 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 1310266 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 62969983500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.480306 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 1210961 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 48438440000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.480306 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 1210961 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 2521227 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000.009497 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 1310266 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 62969983500 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.480306 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 1210961 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 48438440000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.480306 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 1210961 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 664073 # number of replacements
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system.cpu.l2cache.sampled_refs 680479 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 17213.177564 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 2329892 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 921652677000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 481653 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 3444663136 # number of cpu cycles simulated
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system.cpu.num_insts 1495700470 # Number of instructions executed
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system.cpu.num_refs 533262337 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
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---------- End Simulation Statistics ----------
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