1701 lines
198 KiB
Text
1701 lines
198 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.826844 # Number of seconds simulated
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sim_ticks 2826844351500 # Number of ticks simulated
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final_tick 2826844351500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 74392 # Simulator instruction rate (inst/s)
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host_op_rate 90233 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1857645684 # Simulator tick rate (ticks/s)
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host_mem_usage 566256 # Number of bytes of host memory used
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host_seconds 1521.74 # Real time elapsed on the host
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sim_insts 113204796 # Number of instructions simulated
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sim_ops 137311416 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9514916 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 10841588 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 5800064 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
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system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
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system.physmem.bytes_written::total 8135924 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 149190 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 172164 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 90626 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
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system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 131231 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 468384 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3365914 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3835226 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 468384 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 468384 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2051780 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2878094 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2051780 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 468384 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 3372113 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6713320 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 172165 # Number of read requests accepted
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system.physmem.writeReqs 131231 # Number of write requests accepted
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system.physmem.readBursts 172165 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 131231 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 11009408 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue
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system.physmem.bytesWritten 8149760 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 10841652 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 8135924 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 10989 # Per bank write bursts
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system.physmem.perBankRdBursts::1 10130 # Per bank write bursts
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system.physmem.perBankRdBursts::2 11201 # Per bank write bursts
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system.physmem.perBankRdBursts::3 11419 # Per bank write bursts
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system.physmem.perBankRdBursts::4 13122 # Per bank write bursts
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system.physmem.perBankRdBursts::5 10546 # Per bank write bursts
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system.physmem.perBankRdBursts::6 11171 # Per bank write bursts
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system.physmem.perBankRdBursts::7 11539 # Per bank write bursts
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system.physmem.perBankRdBursts::8 10356 # Per bank write bursts
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system.physmem.perBankRdBursts::9 11056 # Per bank write bursts
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system.physmem.perBankRdBursts::10 10496 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9259 # Per bank write bursts
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system.physmem.perBankRdBursts::12 10183 # Per bank write bursts
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system.physmem.perBankRdBursts::13 10761 # Per bank write bursts
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system.physmem.perBankRdBursts::14 10049 # Per bank write bursts
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system.physmem.perBankRdBursts::15 9745 # Per bank write bursts
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system.physmem.perBankWrBursts::0 8312 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7765 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8704 # Per bank write bursts
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system.physmem.perBankWrBursts::3 8604 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7611 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7949 # Per bank write bursts
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system.physmem.perBankWrBursts::6 8258 # Per bank write bursts
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system.physmem.perBankWrBursts::7 8579 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7843 # Per bank write bursts
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system.physmem.perBankWrBursts::9 8531 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7842 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6872 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7611 # Per bank write bursts
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system.physmem.perBankWrBursts::13 8198 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7543 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7118 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 5 # Number of times write queue was full causing retry
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system.physmem.totGap 2826844140500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 541 # Read request sizes (log2)
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system.physmem.readPktSize::3 14 # Read request sizes (log2)
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system.physmem.readPktSize::4 2993 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 168617 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 4381 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 126850 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 151969 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 16016 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 3231 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 789 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1968 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2544 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5739 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 6276 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 6540 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 7277 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 7536 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::22 8095 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 8630 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 9476 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 8902 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 8388 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 7977 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 7946 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 6912 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 6791 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 6777 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 6632 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 149 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 93 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::47 87 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 87 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 78 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 61 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 65 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 62147 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 308.286868 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 180.931959 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 329.707872 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 23391 37.64% 37.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 14782 23.79% 61.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 6350 10.22% 71.64% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::384-511 3679 5.92% 77.56% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::512-639 2602 4.19% 81.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 1532 2.47% 84.21% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::768-895 1126 1.81% 86.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1130 1.82% 87.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 7555 12.16% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 62147 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 6420 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 26.793614 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 556.638433 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-2047 6418 99.97% 99.97% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::total 6420 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 6420 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 19.834891 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 18.369444 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::stdev 11.492928 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::16-19 5612 87.41% 87.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 54 0.84% 88.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 30 0.47% 88.72% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 211 3.29% 92.01% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 221 3.44% 95.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 14 0.22% 95.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 13 0.20% 95.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 15 0.23% 96.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 17 0.26% 96.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 4 0.06% 96.43% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 3 0.05% 96.48% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 5 0.08% 96.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 167 2.60% 99.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 7 0.11% 99.27% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 3 0.05% 99.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 4 0.06% 99.38% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::80-83 10 0.16% 99.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 1 0.02% 99.55% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 1 0.02% 99.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 5 0.08% 99.64% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 4 0.06% 99.70% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-107 2 0.03% 99.74% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 2 0.03% 99.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 4 0.06% 99.83% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::116-119 3 0.05% 99.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-123 1 0.02% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 3 0.05% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 6420 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 2072280000 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 5297692500 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 860110000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 12046.60 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 30796.60 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 27.07 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 142002 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 95212 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 74.76 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 9317341.50 # Average gap between requests
|
|
system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 2694665773000 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 94394300000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 37784264500 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem.actEnergy::0 245987280 # Energy for activate commands per rank (pJ)
|
|
system.physmem.actEnergy::1 223844040 # Energy for activate commands per rank (pJ)
|
|
system.physmem.preEnergy::0 134219250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.preEnergy::1 122137125 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.readEnergy::0 702912600 # Energy for read commands per rank (pJ)
|
|
system.physmem.readEnergy::1 638851200 # Energy for read commands per rank (pJ)
|
|
system.physmem.writeEnergy::0 426267360 # Energy for write commands per rank (pJ)
|
|
system.physmem.writeEnergy::1 398895840 # Energy for write commands per rank (pJ)
|
|
system.physmem.refreshEnergy::0 184635250800 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.refreshEnergy::1 184635250800 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.actBackEnergy::0 80264555415 # Energy for active background per rank (pJ)
|
|
system.physmem.actBackEnergy::1 79079779350 # Energy for active background per rank (pJ)
|
|
system.physmem.preBackEnergy::0 1625694839250 # Energy for precharge background per rank (pJ)
|
|
system.physmem.preBackEnergy::1 1626734116500 # Energy for precharge background per rank (pJ)
|
|
system.physmem.totalEnergy::0 1892104031955 # Total energy per rank (pJ)
|
|
system.physmem.totalEnergy::1 1891832874855 # Total energy per rank (pJ)
|
|
system.physmem.averagePower::0 669.336036 # Core power per rank (mW)
|
|
system.physmem.averagePower::1 669.240113 # Core power per rank (mW)
|
|
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
|
system.cpu.branchPred.lookups 46964274 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 24050124 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 1232745 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 29560624 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 21375180 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 72.309637 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 11765118 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 33710 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.checker.dtb.read_hits 24601402 # DTB read hits
|
|
system.cpu.checker.dtb.read_misses 8241 # DTB read misses
|
|
system.cpu.checker.dtb.write_hits 19645330 # DTB write hits
|
|
system.cpu.checker.dtb.write_misses 1441 # DTB write misses
|
|
system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed
|
|
system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
|
|
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.checker.dtb.flush_entries 4295 # Number of entries that have been flushed from TLB
|
|
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.checker.dtb.prefetch_faults 1773 # Number of TLB faults due to prefetch
|
|
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.checker.dtb.read_accesses 24609643 # DTB read accesses
|
|
system.cpu.checker.dtb.write_accesses 19646771 # DTB write accesses
|
|
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.checker.dtb.hits 44246732 # DTB hits
|
|
system.cpu.checker.dtb.misses 9682 # DTB misses
|
|
system.cpu.checker.dtb.accesses 44256414 # DTB accesses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.checker.itb.inst_hits 115909165 # ITB inst hits
|
|
system.cpu.checker.itb.inst_misses 4826 # ITB inst misses
|
|
system.cpu.checker.itb.read_hits 0 # DTB read hits
|
|
system.cpu.checker.itb.read_misses 0 # DTB read misses
|
|
system.cpu.checker.itb.write_hits 0 # DTB write hits
|
|
system.cpu.checker.itb.write_misses 0 # DTB write misses
|
|
system.cpu.checker.itb.flush_tlb 128 # Number of times complete TLB was flushed
|
|
system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
|
|
system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.checker.itb.flush_entries 2977 # Number of entries that have been flushed from TLB
|
|
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.checker.itb.inst_accesses 115913991 # ITB inst accesses
|
|
system.cpu.checker.itb.hits 115909165 # DTB hits
|
|
system.cpu.checker.itb.misses 4826 # DTB misses
|
|
system.cpu.checker.itb.accesses 115913991 # DTB accesses
|
|
system.cpu.checker.numCycles 139167829 # number of cpu cycles simulated
|
|
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 25471879 # DTB read hits
|
|
system.cpu.dtb.read_misses 60408 # DTB read misses
|
|
system.cpu.dtb.write_hits 19919747 # DTB write hits
|
|
system.cpu.dtb.write_misses 9388 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 1300 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 25532287 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 19929135 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 45391626 # DTB hits
|
|
system.cpu.dtb.misses 69796 # DTB misses
|
|
system.cpu.dtb.accesses 45461422 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 66240582 # ITB inst hits
|
|
system.cpu.itb.inst_misses 11936 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 128 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 66252518 # ITB inst accesses
|
|
system.cpu.itb.hits 66240582 # DTB hits
|
|
system.cpu.itb.misses 11936 # DTB misses
|
|
system.cpu.itb.accesses 66252518 # DTB accesses
|
|
system.cpu.numCycles 260548868 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 104909639 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 184558460 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 46964274 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 33140298 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 145575332 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 6162234 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 168611 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.MiscStallCycles 8187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 338898 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 503455 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 66240894 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 4991 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 254585351 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.884453 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.237226 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 155338707 61.02% 61.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 29243843 11.49% 72.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 14083345 5.53% 78.04% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 55919456 21.96% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 254585351 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.180251 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.708345 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 78108823 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 105363724 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 64680632 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 3828797 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 2603375 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 3422156 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 485996 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 157495015 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 3691306 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 2603375 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 83949795 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 10013130 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 74489960 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 62673363 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 20855728 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 146845952 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 950144 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 437842 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 62734 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 16405 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 18093439 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 150530803 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 678954009 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 164472740 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 141875467 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 8655333 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 2847772 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 2651529 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 13851116 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 26418132 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 21304063 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1686589 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 2099460 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 143580575 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2120859 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 143376028 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 269119 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 6250781 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 14651223 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 125281 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 254585351 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.563175 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 0.882138 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 166207835 65.29% 65.29% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 45306594 17.80% 83.08% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 31956972 12.55% 95.63% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 10300343 4.05% 99.68% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 813574 0.32% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 254585351 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 7371879 32.63% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 5632028 24.93% 57.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 9586948 42.44% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 96038086 66.98% 66.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 113978 0.08% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 26200986 18.27% 85.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 21012051 14.66% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 143376028 # Type of FU issued
|
|
system.cpu.iq.rate 0.550285 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 22590887 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.157564 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 564161758 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 151957264 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 140260479 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 35655 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 165941227 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 23351 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 324401 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1489874 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 18271 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 701002 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 87957 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 6348 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 2603375 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 948323 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 290944 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 145902361 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 26418132 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 21304063 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1096021 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 256072 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 18271 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 317509 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 471618 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 789127 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 142433599 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 25799978 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 872737 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 200927 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 46682549 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 26544085 # Number of branches executed
|
|
system.cpu.iew.exec_stores 20882571 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.546668 # Inst execution rate
|
|
system.cpu.iew.wb_sent 142046516 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 140271910 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 63301578 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 95887209 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.538371 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.660167 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 7591975 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 1995578 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 755003 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 251649065 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.546262 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.145555 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 178084267 70.77% 70.77% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 43398054 17.25% 88.01% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 15481884 6.15% 94.16% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 4357721 1.73% 95.90% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 6462022 2.57% 98.46% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1589357 0.63% 99.10% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 777637 0.31% 99.40% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 414343 0.16% 99.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 1083780 0.43% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 251649065 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 113359701 # Number of instructions committed
|
|
system.cpu.commit.committedOps 137466321 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 45531319 # Number of memory references committed
|
|
system.cpu.commit.loads 24928258 # Number of loads committed
|
|
system.cpu.commit.membars 814674 # Number of memory barriers committed
|
|
system.cpu.commit.branches 26060472 # Number of branches committed
|
|
system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 120282111 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 4896381 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 91813423 66.79% 66.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 24928258 18.13% 85.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 20603061 14.99% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 137466321 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 1083780 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 373370450 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 293050441 # The number of ROB writes
|
|
system.cpu.timesIdled 892831 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 5963517 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 5393139836 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 113204796 # Number of Instructions Simulated
|
|
system.cpu.committedOps 137311416 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 2.301571 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.301571 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.434486 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.434486 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 155870535 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 88662744 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 9591 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 503158962 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 53196475 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 444136009 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1521560 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 837744 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 40170152 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 838256 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 47.921103 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 179419983 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 179419983 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 23329792 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 23329792 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 15588565 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 15588565 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 38918357 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 38918357 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 39265000 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 39265000 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 700458 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 700458 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 3573865 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 3573865 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 4274323 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 4274323 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 4451395 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 4451395 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897569146 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 9897569146 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 135184782788 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 135184782788 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357043749 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 357043749 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 145082351934 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 145082351934 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 145082351934 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 145082351934 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 24030250 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 24030250 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 19162430 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 19162430 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 43192680 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 43192680 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 43716395 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 43716395 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.139346 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.139346 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.934328 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.934328 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.918609 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.918609 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33942.767529 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 33942.767529 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.558498 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 32592.558498 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 504099 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.762558 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 695413 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 695413 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286304 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 286304 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274603 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3274603 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3560907 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 3560907 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3560907 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 3560907 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414154 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 414154 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 713416 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 713416 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 832722 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 832722 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5341815166 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5341815166 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883724205 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883724205 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479869001 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479869001 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225539371 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 17225539371 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18705408372 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 18705408372 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792724250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792724250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440459453 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440459453 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233183703 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233183703 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.137326 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.137326 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39710.100865 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39710.100865 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.978015 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.978015 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.154259 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.154259 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.968880 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.968880 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 1894031 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 511.373814 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 64256441 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1894543 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 33.916591 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 511.373814 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 68132454 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 68132454 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 64256441 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 64256441 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 64256441 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 64256441 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 64256441 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 64256441 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1981452 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1981452 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1981452 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1981452 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1981452 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1981452 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 26762198879 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 26762198879 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 26762198879 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 26762198879 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 26762198879 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 26762198879 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 66237893 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 66237893 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 66237893 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 66237893 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 66237893 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 66237893 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029914 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.029914 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.029914 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.029914 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.029914 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.029914 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.357398 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13506.357398 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.357398 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13506.357398 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.357398 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13506.357398 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 1929 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 105 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 18.371429 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86889 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 86889 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 86889 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 86889 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 86889 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 86889 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894563 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1894563 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1894563 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1894563 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1894563 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1894563 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22159944091 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 22159944091 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22159944091 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 22159944091 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22159944091 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 22159944091 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.599211 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.599211 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.599211 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.599211 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.599211 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.599211 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 98619 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65077.788294 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 3020947 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 163832 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 18.439298 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540884 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218344 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798460 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612666 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617940 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.756264 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000156 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157327 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.079218 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.993008 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65200 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2968 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7006 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55046 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 28437271 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 28437271 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53838 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11660 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1874564 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 528034 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2468096 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 695413 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 695413 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 34 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 34 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 159688 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 159688 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 53838 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 11660 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1874564 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 687722 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2627784 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 53838 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 11660 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1874564 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 687722 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2627784 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 19966 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 13620 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 33612 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2733 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2733 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 136937 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 136937 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 19966 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 150557 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 170549 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 19966 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 150557 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 170549 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1458500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1499718000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1078687250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 2580400000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 582975 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 582975 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46498 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9923495690 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 9923495690 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1458500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1499718000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 11002182940 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 12503895690 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1458500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1499718000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 11002182940 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 12503895690 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53857 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11667 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894530 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 541654 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2501708 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 695413 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 695413 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2767 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2767 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 296625 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 296625 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53857 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 11667 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1894530 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 838279 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2798333 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53857 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 11667 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1894530 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 838279 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2798333 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000353 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000600 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010539 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025145 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.013436 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987712 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987712 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461650 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.461650 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000353 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000600 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010539 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.179602 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.060947 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000353 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000600 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010539 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.179602 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.060947 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 76763.157895 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76607.142857 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75113.593108 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79198.770191 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76770.201119 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 213.309550 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 213.309550 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23249 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72467.599626 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72467.599626 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 76763.157895 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75113.593108 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73076.528757 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 73315.561452 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 76763.157895 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75113.593108 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73076.528757 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 73315.561452 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 90626 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 90626 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 19 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19941 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13508 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 33475 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2733 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2733 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136937 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 136937 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 19941 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 150445 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 170412 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19941 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 150445 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 170412 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1223500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1247817250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 902981250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152473250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27396733 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27396733 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8210001310 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8210001310 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1223500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1247817250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9112982560 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 10362474560 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1223500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1247817250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9112982560 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 10362474560 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157877000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387482250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545359250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107341000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107341000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157877000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494823250 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652700250 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024938 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013381 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987712 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987712 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461650 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461650 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179469 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060898 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179469 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060898 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62575.460107 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66847.886438 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64300.918596 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.417490 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.417490 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59954.587219 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59954.587219 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2564949 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2564884 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 695413 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795093 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495164 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128717 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 6450154 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121297808 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349473 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215428 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 219909377 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 65488 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 3561849 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 9.010233 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::9 3525400 98.98% 98.98% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::10 36449 1.02% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 3561849 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2502926529 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 2849434655 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1334430859 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 74882707 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 30181 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30181 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 36410 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.999676 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 0.999676 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 327996 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 327996 # Number of data accesses
|
|
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
|
|
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
|
|
system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 220 # number of ReadReq misses
|
|
system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 220 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 220 # number of overall misses
|
|
system.iocache.overall_misses::total 220 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ide 26406377 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 26406377 # number of ReadReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 26406377 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 26406377 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 26406377 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 26406377 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 120028.986364 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 120028.986364 # average ReadReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 120028.986364 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 120028.986364 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 36224 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 14965377 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 14965377 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2230292235 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2230292235 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 14965377 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 14965377 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 14965377 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 14965377 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68024.440909 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 68024.440909 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 67834 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 67833 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 27608 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 27608 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 90626 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 135127 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 135127 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 205 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 300222 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 300222 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 94200000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 1697000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 1357984749 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 1678025205 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|