229 lines
7.9 KiB
C++
229 lines
7.9 KiB
C++
/*
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* Copyright (c) 2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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*/
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#ifndef __INSTRECORD_HH__
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#define __INSTRECORD_HH__
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#include "base/bigint.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "cpu/inst_seq.hh" // for InstSeqNum
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#include "cpu/static_inst.hh"
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#include "sim/sim_object.hh"
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class ThreadContext;
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namespace Trace {
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class InstRecord
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{
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protected:
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Tick when;
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// The following fields are initialized by the constructor and
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// thus guaranteed to be valid.
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ThreadContext *thread;
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// need to make this ref-counted so it doesn't go away before we
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// dump the record
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StaticInstPtr staticInst;
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TheISA::PCState pc;
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StaticInstPtr macroStaticInst;
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// The remaining fields are only valid for particular instruction
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// types (e.g, addresses for memory ops) or when particular
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// options are enabled (e.g., tracing full register contents).
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// Each data field has an associated valid flag to indicate
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// whether the data field is valid.
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/*** @defgroup mem
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* @{
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* Memory request information in the instruction accessed memory.
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* @see mem_valid
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*/
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Addr addr; ///< The address that was accessed
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Addr size; ///< The size of the memory request
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unsigned flags; ///< The flags that were assigned to the request.
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/** @} */
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/** @defgroup data
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* If this instruction wrote any data values they're recorded here
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* WARNING: Instructions are quite loose with with what they write
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* since many instructions write multiple values (e.g. destintation
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* register, flags, status, ...) This only captures the last write.
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* @TODO fix this and record all destintations that an instruction writes
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* @see data_status
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*/
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union {
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uint64_t as_int;
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double as_double;
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} data;
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/** @defgroup fetch_seq
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* This records the serial number that the instruction was fetched in.
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* @see fetch_seq_valid
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*/
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InstSeqNum fetch_seq;
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/** @defgroup commit_seq
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* This records the instruction number that was committed in the pipeline
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* @see cp_seq_valid
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*/
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InstSeqNum cp_seq;
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/** @ingroup data
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* What size of data was written?
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*/
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enum {
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DataInvalid = 0,
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DataInt8 = 1, // set to equal number of bytes
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DataInt16 = 2,
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DataInt32 = 4,
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DataInt64 = 8,
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DataDouble = 3
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} data_status;
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/** @ingroup memory
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* Are the memory fields in the record valid?
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*/
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bool mem_valid;
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/** @ingroup fetch_seq
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* Are the fetch sequence number fields valid?
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*/
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bool fetch_seq_valid;
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/** @ingroup commit_seq
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* Are the commit sequence number fields valid?
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*/
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bool cp_seq_valid;
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/** is the predicate for execution this inst true or false (not execed)?
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*/
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bool predicate;
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public:
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InstRecord(Tick _when, ThreadContext *_thread,
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const StaticInstPtr _staticInst,
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TheISA::PCState _pc,
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const StaticInstPtr _macroStaticInst = NULL)
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: when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
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macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
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fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false),
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fetch_seq_valid(false), cp_seq_valid(false), predicate(true)
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{ }
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virtual ~InstRecord() { }
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void setWhen(Tick new_when) { when = new_when; }
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void setMem(Addr a, Addr s, unsigned f)
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{
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addr = a; size = s; flags = f; mem_valid = true;
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}
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void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; }
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void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; }
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void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
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void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
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void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
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void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
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void setData(int64_t d) { setData((uint64_t)d); }
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void setData(int32_t d) { setData((uint32_t)d); }
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void setData(int16_t d) { setData((uint16_t)d); }
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void setData(int8_t d) { setData((uint8_t)d); }
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void setData(double d) { data.as_double = d; data_status = DataDouble; }
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void setFetchSeq(InstSeqNum seq)
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{ fetch_seq = seq; fetch_seq_valid = true; }
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void setCPSeq(InstSeqNum seq)
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{ cp_seq = seq; cp_seq_valid = true; }
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void setPredicate(bool val) { predicate = val; }
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virtual void dump() = 0;
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public:
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Tick getWhen() const { return when; }
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ThreadContext *getThread() const { return thread; }
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StaticInstPtr getStaticInst() const { return staticInst; }
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TheISA::PCState getPCState() const { return pc; }
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StaticInstPtr getMacroStaticInst() const { return macroStaticInst; }
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Addr getAddr() const { return addr; }
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Addr getSize() const { return size; }
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unsigned getFlags() const { return flags; }
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bool getMemValid() const { return mem_valid; }
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uint64_t getIntData() const { return data.as_int; }
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double getFloatData() const { return data.as_double; }
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int getDataStatus() const { return data_status; }
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InstSeqNum getFetchSeq() const { return fetch_seq; }
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bool getFetchSeqValid() const { return fetch_seq_valid; }
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InstSeqNum getCpSeq() const { return cp_seq; }
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bool getCpSeqValid() const { return cp_seq_valid; }
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};
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class InstTracer : public SimObject
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{
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public:
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InstTracer(const Params *p) : SimObject(p)
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{}
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virtual ~InstTracer()
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{};
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virtual InstRecord *
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getInstRecord(Tick when, ThreadContext *tc,
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const StaticInstPtr staticInst, TheISA::PCState pc,
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const StaticInstPtr macroStaticInst = NULL) = 0;
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};
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} // namespace Trace
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#endif // __INSTRECORD_HH__
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