c4a87f874a
SConscript:
Split off activity/idling code into its own class to do the processing separately.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_params.hh:
Activity stuff. This is mostly for debugging and may be removed later on (or changed to enable/disable activity idling).
cpu/o3/cpu.cc:
Move activity idling stuff mostly into its own class, so it no longer clutters this file.
cpu/o3/cpu.hh:
Move activity idling stuff into its own class.
python/m5/objects/AlphaFullCPU.py:
Add parameter for initial activity value.
--HG--
extra : convert_revision : f32f7cc03895dc07ab57ddba78c5402a1a8b0f1a
522 lines
14 KiB
C++
522 lines
14 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_CPU_HH__
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#define __CPU_O3_CPU_HH__
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#include <iostream>
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#include <list>
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#include <queue>
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#include <set>
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#include <vector>
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "config/full_system.hh"
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#include "cpu/activity.hh"
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#include "cpu/base.hh"
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#include "cpu/cpu_exec_context.hh"
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#include "cpu/o3/comm.hh"
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#include "cpu/o3/cpu_policy.hh"
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#include "cpu/o3/scoreboard.hh"
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#include "cpu/o3/thread_state.hh"
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#include "sim/process.hh"
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template <class>
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class Checker;
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class ExecContext;
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class MemInterface;
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class Process;
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class BaseFullCPU : public BaseCPU
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{
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//Stuff that's pretty ISA independent will go here.
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public:
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typedef BaseCPU::Params Params;
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BaseFullCPU(Params *params);
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void regStats();
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protected:
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int cpu_id;
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};
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template <class Impl>
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class FullO3CPU : public BaseFullCPU
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{
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public:
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// Typedefs from the Impl here.
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typedef typename Impl::CPUPol CPUPolicy;
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typedef typename Impl::Params Params;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef O3ThreadState<Impl> Thread;
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typedef typename std::list<DynInstPtr>::iterator ListIt;
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public:
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enum Status {
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Running,
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Idle,
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Halted,
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Blocked,
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SwitchedOut
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};
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/** Overall CPU status. */
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Status _status;
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private:
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class TickEvent : public Event
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{
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private:
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/** Pointer to the CPU. */
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FullO3CPU<Impl> *cpu;
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public:
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/** Constructs a tick event. */
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TickEvent(FullO3CPU<Impl> *c);
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/** Processes a tick event, calling tick() on the CPU. */
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void process();
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/** Returns the description of the tick event. */
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const char *description();
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};
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/** The tick event used for scheduling CPU ticks. */
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TickEvent tickEvent;
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/** Schedule tick event, regardless of its current state. */
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void scheduleTickEvent(int delay)
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{
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + cycles(delay));
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + cycles(delay));
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}
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/** Unschedule tick event, regardless of its current state. */
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void unscheduleTickEvent()
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{
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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public:
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/** Constructs a CPU with the given parameters. */
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FullO3CPU(Params *params);
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/** Destructor. */
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~FullO3CPU();
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/** Registers statistics. */
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void fullCPURegStats();
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/** Ticks CPU, calling tick() on each stage, and checking the overall
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* activity to see if the CPU should deschedule itself.
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*/
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void tick();
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/** Initialize the CPU */
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void init();
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/** Setup CPU to insert a thread's context */
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void insertThread(unsigned tid);
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/** Remove all of a thread's context from CPU */
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void removeThread(unsigned tid);
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/** Count the Total Instructions Committed in the CPU. */
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virtual Counter totalInstructions() const
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{
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Counter total(0);
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for (int i=0; i < thread.size(); i++)
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total += thread[i]->numInst;
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return total;
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}
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/** Add Thread to Active Threads List. */
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void activateContext(int tid, int delay);
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/** Remove Thread from Active Threads List */
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void suspendContext(int tid);
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/** Remove Thread from Active Threads List &&
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* Remove Thread Context from CPU.
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*/
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void deallocateContext(int tid);
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/** Remove Thread from Active Threads List &&
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* Remove Thread Context from CPU.
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*/
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void haltContext(int tid);
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/** Activate a Thread When CPU Resources are Available. */
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void activateWhenReady(int tid);
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/** Add or Remove a Thread Context in the CPU. */
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void doContextSwitch();
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/** Update The Order In Which We Process Threads. */
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void updateThreadPriority();
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/** Executes a syscall on this cycle.
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* ---------------------------------------
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* Note: this is a virtual function. CPU-Specific
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* functionality defined in derived classes
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*/
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virtual void syscall(int tid) { panic("Unimplemented!"); }
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/** Check if there are any system calls pending. */
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void checkSyscalls();
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/** Switches out this CPU.
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*/
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void switchOut(Sampler *sampler);
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void signalSwitched();
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/** Takes over from another CPU.
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*/
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void takeOverFrom(BaseCPU *oldCPU);
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/** Get the current instruction sequence number, and increment it. */
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InstSeqNum getAndIncrementInstSeq()
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{ return globalSeqNum++; }
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#if FULL_SYSTEM
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/** Check if this address is a valid instruction address. */
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bool validInstAddr(Addr addr) { return true; }
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/** Check if this address is a valid data address. */
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bool validDataAddr(Addr addr) { return true; }
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/** Get instruction asid. */
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int getInstAsid(unsigned tid)
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{ return regFile.miscRegs[tid].getInstAsid(); }
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/** Get data asid. */
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int getDataAsid(unsigned tid)
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{ return regFile.miscRegs[tid].getDataAsid(); }
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#else
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/** Check if this address is a valid instruction address. */
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bool validInstAddr(Addr addr,unsigned tid)
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{ return thread[tid]->validInstAddr(addr); }
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/** Check if this address is a valid data address. */
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bool validDataAddr(Addr addr,unsigned tid)
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{ return thread[tid]->validDataAddr(addr); }
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/** Get instruction asid. */
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int getInstAsid(unsigned tid)
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{ return thread[tid]->asid; }
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/** Get data asid. */
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int getDataAsid(unsigned tid)
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{ return thread[tid]->asid; }
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#endif
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//
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// New accessors for new decoder.
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//
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uint64_t readIntReg(int reg_idx);
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float readFloatRegSingle(int reg_idx);
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double readFloatRegDouble(int reg_idx);
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uint64_t readFloatRegInt(int reg_idx);
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void setIntReg(int reg_idx, uint64_t val);
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void setFloatRegSingle(int reg_idx, float val);
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void setFloatRegDouble(int reg_idx, double val);
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void setFloatRegInt(int reg_idx, uint64_t val);
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uint64_t readArchIntReg(int reg_idx, unsigned tid);
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float readArchFloatRegSingle(int reg_idx, unsigned tid);
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double readArchFloatRegDouble(int reg_idx, unsigned tid);
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uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
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void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
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void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
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void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
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void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
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uint64_t readPC(unsigned tid);
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void setPC(Addr new_PC,unsigned tid);
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uint64_t readNextPC(unsigned tid);
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void setNextPC(uint64_t val,unsigned tid);
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/** Function to add instruction onto the head of the list of the
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* instructions. Used when new instructions are fetched.
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*/
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ListIt addInst(DynInstPtr &inst);
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/** Function to tell the CPU that an instruction has completed. */
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void instDone(unsigned tid);
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/** Add Instructions to the CPU Remove List*/
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void addToRemoveList(DynInstPtr &inst);
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/** Remove an instruction from the front end of the list. There's
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* no restriction on location of the instruction.
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*/
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void removeFrontInst(DynInstPtr &inst);
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/** Remove all instructions that are not currently in the ROB. */
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void removeInstsNotInROB(unsigned tid);
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/** Remove all instructions younger than the given sequence number. */
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void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
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inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
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void cleanUpRemovedInsts();
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/** Remove all instructions from the list. */
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// void removeAllInsts();
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void dumpInsts();
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/** Basically a wrapper function so that instructions executed at
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* commit can tell the instruction queue that they have
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* completed. Eventually this hack should be removed.
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*/
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// void wakeDependents(DynInstPtr &inst);
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public:
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/** List of all the instructions in flight. */
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std::list<DynInstPtr> instList;
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/** List of all the instructions that will be removed at the end of this
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* cycle.
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*/
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std::queue<ListIt> removeList;
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#ifdef DEBUG
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std::set<InstSeqNum> snList;
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#endif
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/** Records if instructions need to be removed this cycle due to
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* being retired or squashed.
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*/
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bool removeInstsThisCycle;
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protected:
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/** The fetch stage. */
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typename CPUPolicy::Fetch fetch;
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/** The decode stage. */
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typename CPUPolicy::Decode decode;
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/** The dispatch stage. */
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typename CPUPolicy::Rename rename;
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/** The issue/execute/writeback stages. */
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typename CPUPolicy::IEW iew;
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/** The commit stage. */
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typename CPUPolicy::Commit commit;
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/** The register file. */
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typename CPUPolicy::RegFile regFile;
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/** The free list. */
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typename CPUPolicy::FreeList freeList;
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/** The rename map. */
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typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
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/** The commit rename map. */
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typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
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/** The re-order buffer. */
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typename CPUPolicy::ROB rob;
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/** Active Threads List */
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std::list<unsigned> activeThreads;
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/** Integer Register Scoreboard */
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Scoreboard scoreboard;
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public:
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/** Enum to give each stage a specific index, so when calling
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* activateStage() or deactivateStage(), they can specify which stage
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* is being activated/deactivated.
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*/
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enum StageIdx {
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FetchIdx,
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DecodeIdx,
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RenameIdx,
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IEWIdx,
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CommitIdx,
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NumStages };
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/** Typedefs from the Impl to get the structs that each of the
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* time buffers should use.
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*/
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typedef typename CPUPolicy::TimeStruct TimeStruct;
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typedef typename CPUPolicy::FetchStruct FetchStruct;
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typedef typename CPUPolicy::DecodeStruct DecodeStruct;
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typedef typename CPUPolicy::RenameStruct RenameStruct;
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typedef typename CPUPolicy::IEWStruct IEWStruct;
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/** The main time buffer to do backwards communication. */
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TimeBuffer<TimeStruct> timeBuffer;
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/** The fetch stage's instruction queue. */
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TimeBuffer<FetchStruct> fetchQueue;
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/** The decode stage's instruction queue. */
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TimeBuffer<DecodeStruct> decodeQueue;
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/** The rename stage's instruction queue. */
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TimeBuffer<RenameStruct> renameQueue;
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/** The IEW stage's instruction queue. */
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TimeBuffer<IEWStruct> iewQueue;
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public:
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ActivityRecorder activityRec;
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void activityThisCycle() { activityRec.activity(); }
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void activateStage(const StageIdx idx)
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{ activityRec.activateStage(idx); }
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void deactivateStage(const StageIdx idx)
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{ activityRec.deactivateStage(idx); }
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/** Wakes the CPU, rescheduling the CPU if it's not already active. */
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void wakeCPU();
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/** Gets a free thread id. Use if thread ids change across system. */
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int getFreeTid();
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public:
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/** Temporary function to get pointer to exec context. */
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ExecContext *xcBase(unsigned tid)
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{
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return thread[tid]->getXCProxy();
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}
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/** The global sequence number counter. */
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InstSeqNum globalSeqNum;
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Checker<DynInstPtr> *checker;
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#if FULL_SYSTEM
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/** Pointer to the system. */
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System *system;
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/** Pointer to the memory controller. */
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MemoryController *memCtrl;
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/** Pointer to physical memory. */
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PhysicalMemory *physmem;
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#endif
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/** Pointer to memory. */
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FunctionalMemory *mem;
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Sampler *sampler;
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int switchCount;
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// List of all ExecContexts.
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std::vector<Thread *> thread;
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#if 0
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/** Page table pointer. */
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PageTable *pTable;
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#endif
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/** Pointer to the icache interface. */
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MemInterface *icacheInterface;
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/** Pointer to the dcache interface. */
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MemInterface *dcacheInterface;
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/** Whether or not the CPU should defer its registration. */
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bool deferRegistration;
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/** Is there a context switch pending? */
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bool contextSwitch;
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/** Threads Scheduled to Enter CPU */
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std::list<int> cpuWaitList;
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/** The cycle that the CPU was last running, used for statistics. */
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Tick lastRunningCycle;
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/** Number of Threads CPU can process */
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unsigned numThreads;
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/** Mapping for system thread id to cpu id */
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std::map<unsigned,unsigned> threadMap;
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/** Available thread ids in the cpu*/
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std::vector<unsigned> tids;
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/** Stat for total number of times the CPU is descheduled. */
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Stats::Scalar<> timesIdled;
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/** Stat for total number of cycles the CPU spends descheduled. */
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Stats::Scalar<> idleCycles;
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/** Stat for the number of committed instructions per thread. */
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Stats::Vector<> committedInsts;
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/** Stat for the total number of committed instructions. */
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Stats::Scalar<> totalCommittedInsts;
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/** Stat for the CPI per thread. */
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Stats::Formula cpi;
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/** Stat for the total CPI. */
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Stats::Formula totalCpi;
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/** Stat for the IPC per thread. */
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Stats::Formula ipc;
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/** Stat for the total IPC. */
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Stats::Formula totalIpc;
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};
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#endif // __CPU_O3_CPU_HH__
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