ff3d16ca1f
arch/alpha/ev5.cc: Move kernel stats out of CPU and into XC. Also be sure to check if the kernel stats exist prior to using them. --HG-- extra : convert_revision : 565cd7026410fd7d8586f953d9b328c2e67a9473
776 lines
20 KiB
C++
776 lines
20 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/alpha/faults.hh"
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#include "base/cprintf.hh"
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "cpu/checker/exec_context.hh"
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#include "mem/mem_interface.hh"
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#include "sim/sim_events.hh"
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#include "sim/stats.hh"
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#include "cpu/o3/alpha_cpu.hh"
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#include "cpu/o3/alpha_params.hh"
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#include "cpu/o3/comm.hh"
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#include "cpu/o3/thread_state.hh"
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#if FULL_SYSTEM
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#include "arch/alpha/osfpal.hh"
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#include "arch/isa_traits.hh"
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#include "cpu/quiesce_event.hh"
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#include "kern/kernel_stats.hh"
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#endif
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using namespace TheISA;
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template <class Impl>
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AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
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#if FULL_SYSTEM
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: FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb)
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#else
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: FullO3CPU<Impl>(params)
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#endif
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{
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DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n");
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this->thread.resize(this->numThreads);
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for (int i = 0; i < this->numThreads; ++i) {
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#if FULL_SYSTEM
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assert(this->numThreads == 1);
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this->thread[i] = new Thread(this, 0, params->mem);
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this->thread[i]->setStatus(ExecContext::Suspended);
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#else
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if (i < params->workload.size()) {
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DPRINTF(FullCPU, "FullCPU: Workload[%i]'s starting PC is %#x, "
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"process is %#x",
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i, params->workload[i]->prog_entry, this->thread[i]);
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this->thread[i] = new Thread(this, i, params->workload[i], i);
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assert(params->workload[i]->getMemory() != NULL);
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this->thread[i]->setStatus(ExecContext::Suspended);
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//usedTids[i] = true;
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//threadMap[i] = i;
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} else {
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//Allocate Empty execution context so M5 can use later
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//when scheduling threads to CPU
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Process* dummy_proc = NULL;
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this->thread[i] = new Thread(this, i, dummy_proc, i);
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//usedTids[i] = false;
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}
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#endif // !FULL_SYSTEM
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this->thread[i]->numInst = 0;
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ExecContext *xc_proxy;
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AlphaXC *alpha_xc_proxy = new AlphaXC;
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if (params->checker) {
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xc_proxy = new CheckerExecContext<AlphaXC>(alpha_xc_proxy, this->checker);
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} else {
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xc_proxy = alpha_xc_proxy;
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}
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alpha_xc_proxy->cpu = this;
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alpha_xc_proxy->thread = this->thread[i];
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#if FULL_SYSTEM
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this->thread[i]->quiesceEvent =
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new EndQuiesceEvent(xc_proxy);
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this->thread[i]->lastActivate = 0;
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this->thread[i]->lastSuspend = 0;
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#endif
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this->thread[i]->xcProxy = xc_proxy;
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this->execContexts.push_back(xc_proxy);
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}
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for (int i=0; i < this->numThreads; i++) {
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this->thread[i]->funcExeInst = 0;
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}
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// Sets CPU pointers. These must be set at this level because the CPU
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// pointers are defined to be the highest level of CPU class.
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this->fetch.setCPU(this);
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this->decode.setCPU(this);
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this->rename.setCPU(this);
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this->iew.setCPU(this);
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this->commit.setCPU(this);
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this->rob.setCPU(this);
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this->regFile.setCPU(this);
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lockAddr = 0;
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lockFlag = false;
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::regStats()
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{
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// Register stats for everything that has stats.
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this->fullCPURegStats();
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this->fetch.regStats();
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this->decode.regStats();
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this->rename.regStats();
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this->iew.regStats();
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this->commit.regStats();
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}
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#if FULL_SYSTEM
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::dumpFuncProfile()
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{
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// Currently not supported
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}
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#endif
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
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{
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// some things should already be set up
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assert(getMemPtr() == old_context->getMemPtr());
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#if FULL_SYSTEM
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assert(getSystemPtr() == old_context->getSystemPtr());
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#else
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assert(getProcessPtr() == old_context->getProcessPtr());
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#endif
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// copy over functional state
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setStatus(old_context->status());
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copyArchRegs(old_context);
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setCpuId(old_context->readCpuId());
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#if !FULL_SYSTEM
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thread->funcExeInst = old_context->readFuncExeInst();
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#else
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EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
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if (other_quiesce) {
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// Point the quiesce event's XC at this XC so that it wakes up
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// the proper CPU.
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other_quiesce->xc = this;
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}
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if (thread->quiesceEvent) {
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thread->quiesceEvent->xc = this;
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}
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// Transfer kernel stats from one CPU to the other.
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thread->kernelStats = old_context->getKernelStats();
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// storeCondFailures = 0;
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cpu->lockFlag = false;
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#endif
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old_context->setStatus(ExecContext::Unallocated);
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thread->inSyscall = false;
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thread->trapPending = false;
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::activate(int delay)
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{
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DPRINTF(FullCPU, "Calling activate on AlphaXC\n");
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if (thread->status() == ExecContext::Active)
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return;
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#if FULL_SYSTEM
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thread->lastActivate = curTick;
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#endif
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if (thread->status() == ExecContext::Unallocated) {
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cpu->activateWhenReady(thread->tid);
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return;
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}
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thread->setStatus(ExecContext::Active);
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// status() == Suspended
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cpu->activateContext(thread->tid, delay);
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::suspend()
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{
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DPRINTF(FullCPU, "Calling suspend on AlphaXC\n");
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if (thread->status() == ExecContext::Suspended)
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return;
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#if FULL_SYSTEM
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thread->lastActivate = curTick;
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thread->lastSuspend = curTick;
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#endif
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/*
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#if FULL_SYSTEM
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// Don't change the status from active if there are pending interrupts
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if (cpu->check_interrupts()) {
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assert(status() == ExecContext::Active);
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return;
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}
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#endif
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*/
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thread->setStatus(ExecContext::Suspended);
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cpu->suspendContext(thread->tid);
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::deallocate()
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{
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DPRINTF(FullCPU, "Calling deallocate on AlphaXC\n");
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if (thread->status() == ExecContext::Unallocated)
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return;
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thread->setStatus(ExecContext::Unallocated);
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cpu->deallocateContext(thread->tid);
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::halt()
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{
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DPRINTF(FullCPU, "Calling halt on AlphaXC\n");
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if (thread->status() == ExecContext::Halted)
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return;
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thread->setStatus(ExecContext::Halted);
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cpu->haltContext(thread->tid);
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::regStats(const std::string &name)
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{
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#if FULL_SYSTEM
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thread->kernelStats = new Kernel::Statistics(cpu->system);
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thread->kernelStats->regStats(name + ".kern");
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#endif
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::serialize(std::ostream &os)
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{
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#if FULL_SYSTEM
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if (thread->kernelStats)
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thread->kernelStats->serialize(os);
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#endif
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::unserialize(Checkpoint *cp, const std::string §ion)
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{
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#if FULL_SYSTEM
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if (thread->kernelStats)
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thread->kernelStats->unserialize(cp, section);
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#endif
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}
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#if FULL_SYSTEM
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template <class Impl>
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EndQuiesceEvent *
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AlphaFullCPU<Impl>::AlphaXC::getQuiesceEvent()
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{
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return thread->quiesceEvent;
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}
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template <class Impl>
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Tick
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AlphaFullCPU<Impl>::AlphaXC::readLastActivate()
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{
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return thread->lastActivate;
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}
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template <class Impl>
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Tick
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AlphaFullCPU<Impl>::AlphaXC::readLastSuspend()
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{
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return thread->lastSuspend;
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::profileClear()
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{}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::profileSample()
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{}
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#endif
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template <class Impl>
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TheISA::MachInst
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AlphaFullCPU<Impl>::AlphaXC:: getInst()
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{
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return thread->inst;
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::copyArchRegs(ExecContext *xc)
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{
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// This function will mess things up unless the ROB is empty and
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// there are no instructions in the pipeline.
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unsigned tid = thread->tid;
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PhysRegIndex renamed_reg;
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// First loop through the integer registers.
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for (int i = 0; i < AlphaISA::NumIntRegs; ++i) {
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renamed_reg = cpu->renameMap[tid].lookup(i);
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DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
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"now has data %lli.\n",
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renamed_reg, cpu->readIntReg(renamed_reg),
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xc->readIntReg(i));
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cpu->setIntReg(renamed_reg, xc->readIntReg(i));
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) {
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renamed_reg = cpu->renameMap[tid].lookup(i + AlphaISA::FP_Base_DepTag);
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cpu->setFloatRegDouble(renamed_reg,
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xc->readFloatRegDouble(i));
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cpu->setFloatRegInt(renamed_reg,
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xc->readFloatRegInt(i));
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}
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// Copy the misc regs.
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cpu->regFile.miscRegs[tid].copyMiscRegs(xc);
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// Then finally set the PC and the next PC.
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cpu->setPC(xc->readPC(), tid);
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cpu->setNextPC(xc->readNextPC(), tid);
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#if !FULL_SYSTEM
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this->thread->funcExeInst = xc->readFuncExeInst();
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#endif
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::clearArchRegs()
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{}
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template <class Impl>
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uint64_t
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AlphaFullCPU<Impl>::AlphaXC::readIntReg(int reg_idx)
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{
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DPRINTF(Fault, "Reading int register through the XC!\n");
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return cpu->readArchIntReg(reg_idx, thread->tid);
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}
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template <class Impl>
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float
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AlphaFullCPU<Impl>::AlphaXC::readFloatRegSingle(int reg_idx)
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{
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DPRINTF(Fault, "Reading float register through the XC!\n");
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return cpu->readArchFloatRegSingle(reg_idx, thread->tid);
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}
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template <class Impl>
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double
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AlphaFullCPU<Impl>::AlphaXC::readFloatRegDouble(int reg_idx)
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{
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DPRINTF(Fault, "Reading float register through the XC!\n");
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return cpu->readArchFloatRegDouble(reg_idx, thread->tid);
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}
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template <class Impl>
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uint64_t
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AlphaFullCPU<Impl>::AlphaXC::readFloatRegInt(int reg_idx)
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{
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DPRINTF(Fault, "Reading floatint register through the XC!\n");
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return cpu->readArchFloatRegInt(reg_idx, thread->tid);
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::setIntReg(int reg_idx, uint64_t val)
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{
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DPRINTF(Fault, "Setting int register through the XC!\n");
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cpu->setArchIntReg(reg_idx, val, thread->tid);
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if (!thread->trapPending && !thread->inSyscall) {
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cpu->squashFromXC(thread->tid);
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}
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::setFloatRegSingle(int reg_idx, float val)
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{
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DPRINTF(Fault, "Setting float register through the XC!\n");
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cpu->setArchFloatRegSingle(reg_idx, val, thread->tid);
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if (!thread->trapPending && !thread->inSyscall) {
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cpu->squashFromXC(thread->tid);
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}
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::setFloatRegDouble(int reg_idx, double val)
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{
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DPRINTF(Fault, "Setting float register through the XC!\n");
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cpu->setArchFloatRegDouble(reg_idx, val, thread->tid);
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if (!thread->trapPending && !thread->inSyscall) {
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cpu->squashFromXC(thread->tid);
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}
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::setFloatRegInt(int reg_idx, uint64_t val)
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{
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DPRINTF(Fault, "Setting floatint register through the XC!\n");
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cpu->setArchFloatRegInt(reg_idx, val, thread->tid);
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if (!thread->trapPending && !thread->inSyscall) {
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cpu->squashFromXC(thread->tid);
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}
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::setPC(uint64_t val)
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{
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cpu->setPC(val, thread->tid);
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if (!thread->trapPending && !thread->inSyscall) {
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cpu->squashFromXC(thread->tid);
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}
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::setNextPC(uint64_t val)
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{
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cpu->setNextPC(val, thread->tid);
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if (!thread->trapPending && !thread->inSyscall) {
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cpu->squashFromXC(thread->tid);
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}
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}
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template <class Impl>
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Fault
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AlphaFullCPU<Impl>::AlphaXC::setMiscReg(int misc_reg, const MiscReg &val)
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{
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DPRINTF(Fault, "Setting misc register through the XC!\n");
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Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->tid);
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if (!thread->trapPending && !thread->inSyscall) {
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cpu->squashFromXC(thread->tid);
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}
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return ret_fault;
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}
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template <class Impl>
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Fault
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AlphaFullCPU<Impl>::AlphaXC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
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{
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DPRINTF(Fault, "Setting misc register through the XC!\n");
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Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, thread->tid);
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if (!thread->trapPending && !thread->inSyscall) {
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cpu->squashFromXC(thread->tid);
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}
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return ret_fault;
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}
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#if !FULL_SYSTEM
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template <class Impl>
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TheISA::IntReg
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AlphaFullCPU<Impl>::AlphaXC::getSyscallArg(int i)
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{
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return cpu->getSyscallArg(i, thread->tid);
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::AlphaXC::setSyscallArg(int i, IntReg val)
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{
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cpu->setSyscallArg(i, val, thread->tid);
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}
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template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::AlphaXC::setSyscallReturn(SyscallReturn return_value)
|
|
{
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|
cpu->setSyscallReturn(return_value, thread->tid);
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|
}
|
|
|
|
#endif // FULL_SYSTEM
|
|
|
|
template <class Impl>
|
|
MiscReg
|
|
AlphaFullCPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
|
|
{
|
|
return this->regFile.readMiscReg(misc_reg, tid);
|
|
}
|
|
|
|
template <class Impl>
|
|
MiscReg
|
|
AlphaFullCPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault,
|
|
unsigned tid)
|
|
{
|
|
return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid);
|
|
}
|
|
|
|
template <class Impl>
|
|
Fault
|
|
AlphaFullCPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
|
|
{
|
|
return this->regFile.setMiscReg(misc_reg, val, tid);
|
|
}
|
|
|
|
template <class Impl>
|
|
Fault
|
|
AlphaFullCPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
|
|
unsigned tid)
|
|
{
|
|
return this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::squashFromXC(unsigned tid)
|
|
{
|
|
this->thread[tid]->inSyscall = true;
|
|
this->commit.generateXCEvent(tid);
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::post_interrupt(int int_num, int index)
|
|
{
|
|
BaseCPU::post_interrupt(int_num, index);
|
|
|
|
if (this->thread[0]->status() == ExecContext::Suspended) {
|
|
DPRINTF(IPI,"Suspended Processor awoke\n");
|
|
// xcProxies[0]->activate();
|
|
this->execContexts[0]->activate();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
int
|
|
AlphaFullCPU<Impl>::readIntrFlag()
|
|
{
|
|
return this->regFile.readIntrFlag();
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::setIntrFlag(int val)
|
|
{
|
|
this->regFile.setIntrFlag(val);
|
|
}
|
|
|
|
template <class Impl>
|
|
Fault
|
|
AlphaFullCPU<Impl>::hwrei(unsigned tid)
|
|
{
|
|
// Need to clear the lock flag upon returning from an interrupt.
|
|
this->lockFlag = false;
|
|
|
|
this->thread[tid]->kernelStats->hwrei();
|
|
|
|
this->checkInterrupts = true;
|
|
|
|
// FIXME: XXX check for interrupts? XXX
|
|
return NoFault;
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
AlphaFullCPU<Impl>::simPalCheck(int palFunc, unsigned tid)
|
|
{
|
|
if (this->thread[tid]->kernelStats)
|
|
this->thread[tid]->kernelStats->callpal(palFunc,
|
|
this->execContexts[tid]);
|
|
|
|
switch (palFunc) {
|
|
case PAL::halt:
|
|
halt();
|
|
if (--System::numSystemsRunning == 0)
|
|
new SimExitEvent("all cpus halted");
|
|
break;
|
|
|
|
case PAL::bpt:
|
|
case PAL::bugchk:
|
|
if (this->system->breakpoint())
|
|
return false;
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::trap(Fault fault, unsigned tid)
|
|
{
|
|
fault->invoke(this->execContexts[tid]);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::processInterrupts()
|
|
{
|
|
// Check for interrupts here. For now can copy the code that
|
|
// exists within isa_fullsys_traits.hh. Also assume that thread 0
|
|
// is the one that handles the interrupts.
|
|
// @todo: Possibly consolidate the interrupt checking code.
|
|
// @todo: Allow other threads to handle interrupts.
|
|
|
|
// Check if there are any outstanding interrupts
|
|
//Handle the interrupts
|
|
int ipl = 0;
|
|
int summary = 0;
|
|
|
|
this->checkInterrupts = false;
|
|
|
|
if (this->readMiscReg(IPR_ASTRR, 0))
|
|
panic("asynchronous traps not implemented\n");
|
|
|
|
if (this->readMiscReg(IPR_SIRR, 0)) {
|
|
for (int i = INTLEVEL_SOFTWARE_MIN;
|
|
i < INTLEVEL_SOFTWARE_MAX; i++) {
|
|
if (this->readMiscReg(IPR_SIRR, 0) & (ULL(1) << i)) {
|
|
// See table 4-19 of the 21164 hardware reference
|
|
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
|
|
summary |= (ULL(1) << i);
|
|
}
|
|
}
|
|
}
|
|
|
|
uint64_t interrupts = this->intr_status();
|
|
|
|
if (interrupts) {
|
|
for (int i = INTLEVEL_EXTERNAL_MIN;
|
|
i < INTLEVEL_EXTERNAL_MAX; i++) {
|
|
if (interrupts & (ULL(1) << i)) {
|
|
// See table 4-19 of the 21164 hardware reference
|
|
ipl = i;
|
|
summary |= (ULL(1) << i);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (ipl && ipl > this->readMiscReg(IPR_IPLR, 0)) {
|
|
this->setMiscReg(IPR_ISR, summary, 0);
|
|
this->setMiscReg(IPR_INTID, ipl, 0);
|
|
if (this->checker) {
|
|
this->checker->cpuXCBase()->setMiscReg(IPR_ISR, summary);
|
|
this->checker->cpuXCBase()->setMiscReg(IPR_INTID, ipl);
|
|
}
|
|
this->trap(Fault(new InterruptFault), 0);
|
|
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
|
|
this->readMiscReg(IPR_IPLR, 0), ipl, summary);
|
|
}
|
|
}
|
|
|
|
#endif // FULL_SYSTEM
|
|
|
|
#if !FULL_SYSTEM
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::syscall(int tid)
|
|
{
|
|
DPRINTF(FullCPU, "AlphaFullCPU: [tid:%i] Executing syscall().\n\n", tid);
|
|
|
|
DPRINTF(Activity,"Activity: syscall() called.\n");
|
|
|
|
// Temporarily increase this by one to account for the syscall
|
|
// instruction.
|
|
++(this->thread[tid]->funcExeInst);
|
|
|
|
// Execute the actual syscall.
|
|
this->thread[tid]->syscall();
|
|
|
|
// Decrease funcExeInst by one as the normal commit will handle
|
|
// incrementing it.
|
|
--(this->thread[tid]->funcExeInst);
|
|
}
|
|
|
|
template <class Impl>
|
|
TheISA::IntReg
|
|
AlphaFullCPU<Impl>::getSyscallArg(int i, int tid)
|
|
{
|
|
return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
|
|
{
|
|
this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
|
|
{
|
|
// check for error condition. Alpha syscall convention is to
|
|
// indicate success/failure in reg a3 (r19) and put the
|
|
// return value itself in the standard return value reg (v0).
|
|
if (return_value.successful()) {
|
|
// no error
|
|
this->setArchIntReg(SyscallSuccessReg, 0, tid);
|
|
this->setArchIntReg(ReturnValueReg, return_value.value(), tid);
|
|
} else {
|
|
// got an error, return details
|
|
this->setArchIntReg(SyscallSuccessReg, (IntReg) -1, tid);
|
|
this->setArchIntReg(ReturnValueReg, -return_value.value(), tid);
|
|
}
|
|
}
|
|
#endif
|