949437d559
In cases where we discard the packet, make sure to also delete it and the associated request.
534 lines
19 KiB
C++
534 lines
19 KiB
C++
/*
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* Copyright (c) 2012-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Thomas Grass
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* Andreas Hansson
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* Sascha Bischoff
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*/
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#include <sstream>
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#include "base/intmath.hh"
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#include "base/random.hh"
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#include "cpu/testers/traffic_gen/traffic_gen.hh"
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#include "debug/Checkpoint.hh"
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#include "debug/TrafficGen.hh"
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#include "sim/stats.hh"
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#include "sim/system.hh"
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using namespace std;
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TrafficGen::TrafficGen(const TrafficGenParams* p)
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: MemObject(p),
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system(p->system),
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masterID(system->getMasterId(name())),
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configFile(p->config_file),
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elasticReq(p->elastic_req),
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nextTransitionTick(0),
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nextPacketTick(0),
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currState(0),
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port(name() + ".port", *this),
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retryPkt(NULL),
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retryPktTick(0),
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updateEvent(this)
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{
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}
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TrafficGen*
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TrafficGenParams::create()
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{
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return new TrafficGen(this);
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}
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BaseMasterPort&
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TrafficGen::getMasterPort(const string& if_name, PortID idx)
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{
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if (if_name == "port") {
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return port;
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} else {
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return MemObject::getMasterPort(if_name, idx);
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}
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}
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void
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TrafficGen::init()
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{
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if (!port.isConnected())
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fatal("The port of %s is not connected!\n", name());
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// if the system is in timing mode active the request generator
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if (system->isTimingMode()) {
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DPRINTF(TrafficGen, "Timing mode, activating request generator\n");
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parseConfig();
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// enter initial state
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enterState(currState);
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} else {
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DPRINTF(TrafficGen,
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"Traffic generator is only active in timing mode\n");
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}
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}
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void
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TrafficGen::initState()
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{
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// when not restoring from a checkpoint, make sure we kick things off
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if (system->isTimingMode()) {
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// call nextPacketTick on the state to advance it
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nextPacketTick = states[currState]->nextPacketTick(elasticReq, 0);
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schedule(updateEvent, std::min(nextPacketTick, nextTransitionTick));
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} else {
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DPRINTF(TrafficGen,
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"Traffic generator is only active in timing mode\n");
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}
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}
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DrainState
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TrafficGen::drain()
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{
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if (!updateEvent.scheduled()) {
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// no event has been scheduled yet (e.g. switched from atomic mode)
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return DrainState::Drained;
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}
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if (retryPkt == NULL) {
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// shut things down
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nextPacketTick = MaxTick;
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nextTransitionTick = MaxTick;
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deschedule(updateEvent);
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return DrainState::Drained;
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} else {
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return DrainState::Draining;
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}
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}
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void
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TrafficGen::serialize(CheckpointOut &cp) const
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{
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DPRINTF(Checkpoint, "Serializing TrafficGen\n");
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// save ticks of the graph event if it is scheduled
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Tick nextEvent = updateEvent.scheduled() ? updateEvent.when() : 0;
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DPRINTF(TrafficGen, "Saving nextEvent=%llu\n", nextEvent);
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SERIALIZE_SCALAR(nextEvent);
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SERIALIZE_SCALAR(nextTransitionTick);
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SERIALIZE_SCALAR(nextPacketTick);
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SERIALIZE_SCALAR(currState);
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}
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void
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TrafficGen::unserialize(CheckpointIn &cp)
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{
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// restore scheduled events
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Tick nextEvent;
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UNSERIALIZE_SCALAR(nextEvent);
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if (nextEvent != 0) {
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schedule(updateEvent, nextEvent);
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}
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UNSERIALIZE_SCALAR(nextTransitionTick);
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UNSERIALIZE_SCALAR(nextPacketTick);
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// @todo In the case of a stateful generator state such as the
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// trace player we would also have to restore the position in the
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// trace playback and the tick offset
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UNSERIALIZE_SCALAR(currState);
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}
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void
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TrafficGen::update()
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{
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// if we have reached the time for the next state transition, then
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// perform the transition
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if (curTick() >= nextTransitionTick) {
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transition();
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} else {
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assert(curTick() >= nextPacketTick);
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// get the next packet and try to send it
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PacketPtr pkt = states[currState]->getNextPacket();
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// suppress packets that are not destined for a memory, such as
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// device accesses that could be part of a trace
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if (system->isMemAddr(pkt->getAddr())) {
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numPackets++;
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if (!port.sendTimingReq(pkt)) {
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retryPkt = pkt;
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retryPktTick = curTick();
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}
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} else {
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DPRINTF(TrafficGen, "Suppressed packet %s 0x%x\n",
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pkt->cmdString(), pkt->getAddr());
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delete pkt->req;
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delete pkt;
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pkt = nullptr;
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}
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}
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// if we are waiting for a retry, do not schedule any further
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// events, in the case of a transition or a successful send, go
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// ahead and determine when the next update should take place
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if (retryPkt == NULL) {
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// schedule next update event based on either the next execute
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// tick or the next transition, which ever comes first
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nextPacketTick = states[currState]->nextPacketTick(elasticReq, 0);
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Tick nextEventTick = std::min(nextPacketTick, nextTransitionTick);
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DPRINTF(TrafficGen, "Next event scheduled at %lld\n", nextEventTick);
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schedule(updateEvent, nextEventTick);
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}
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}
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void
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TrafficGen::parseConfig()
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{
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// keep track of the transitions parsed to create the matrix when
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// done
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vector<Transition> transitions;
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// open input file
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ifstream infile;
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infile.open(configFile.c_str(), ifstream::in);
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if (!infile.is_open()) {
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fatal("Traffic generator %s config file not found at %s\n",
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name(), configFile);
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}
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bool init_state_set = false;
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// read line by line and determine the action based on the first
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// keyword
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string keyword;
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string line;
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while (getline(infile, line).good()) {
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// see if this line is a comment line, and if so skip it
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if (line.find('#') != 1) {
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// create an input stream for the tokenization
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istringstream is(line);
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// determine the keyword
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is >> keyword;
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if (keyword == "STATE") {
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// parse the behaviour of this state
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uint32_t id;
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Tick duration;
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string mode;
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is >> id >> duration >> mode;
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if (mode == "TRACE") {
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string traceFile;
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Addr addrOffset;
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is >> traceFile >> addrOffset;
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states[id] = new TraceGen(name(), masterID, duration,
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traceFile, addrOffset);
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DPRINTF(TrafficGen, "State: %d TraceGen\n", id);
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} else if (mode == "IDLE") {
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states[id] = new IdleGen(name(), masterID, duration);
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DPRINTF(TrafficGen, "State: %d IdleGen\n", id);
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} else if (mode == "LINEAR" || mode == "RANDOM" ||
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mode == "DRAM" || mode == "DRAM_ROTATE") {
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uint32_t read_percent;
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Addr start_addr;
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Addr end_addr;
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Addr blocksize;
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Tick min_period;
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Tick max_period;
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Addr data_limit;
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is >> read_percent >> start_addr >> end_addr >>
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blocksize >> min_period >> max_period >> data_limit;
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DPRINTF(TrafficGen, "%s, addr %x to %x, size %d,"
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" period %d to %d, %d%% reads\n",
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mode, start_addr, end_addr, blocksize, min_period,
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max_period, read_percent);
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if (blocksize > system->cacheLineSize())
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fatal("TrafficGen %s block size (%d) is larger than "
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"cache line size (%d)\n", name(),
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blocksize, system->cacheLineSize());
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if (read_percent > 100)
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fatal("%s cannot have more than 100% reads", name());
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if (min_period > max_period)
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fatal("%s cannot have min_period > max_period", name());
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if (mode == "LINEAR") {
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states[id] = new LinearGen(name(), masterID,
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duration, start_addr,
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end_addr, blocksize,
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min_period, max_period,
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read_percent, data_limit);
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DPRINTF(TrafficGen, "State: %d LinearGen\n", id);
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} else if (mode == "RANDOM") {
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states[id] = new RandomGen(name(), masterID,
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duration, start_addr,
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end_addr, blocksize,
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min_period, max_period,
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read_percent, data_limit);
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DPRINTF(TrafficGen, "State: %d RandomGen\n", id);
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} else if (mode == "DRAM" || mode == "DRAM_ROTATE") {
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// stride size (bytes) of the request for achieving
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// required hit length
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unsigned int stride_size;
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unsigned int page_size;
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unsigned int nbr_of_banks_DRAM;
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unsigned int nbr_of_banks_util;
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unsigned int addr_mapping;
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unsigned int nbr_of_ranks;
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is >> stride_size >> page_size >> nbr_of_banks_DRAM >>
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nbr_of_banks_util >> addr_mapping >>
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nbr_of_ranks;
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if (stride_size > page_size)
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warn("DRAM generator stride size (%d) is greater "
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"than page size (%d) of the memory\n",
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blocksize, page_size);
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if (nbr_of_banks_util > nbr_of_banks_DRAM)
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fatal("Attempting to use more banks (%d) than "
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"what is available (%d)\n",
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nbr_of_banks_util, nbr_of_banks_DRAM);
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// count the number of sequential packets to
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// generate
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unsigned int num_seq_pkts = 1;
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if (stride_size > blocksize) {
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num_seq_pkts = divCeil(stride_size, blocksize);
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DPRINTF(TrafficGen, "stride size: %d "
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"block size: %d, num_seq_pkts: %d\n",
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stride_size, blocksize, num_seq_pkts);
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}
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if (mode == "DRAM") {
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states[id] = new DramGen(name(), masterID,
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duration, start_addr,
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end_addr, blocksize,
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min_period, max_period,
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read_percent, data_limit,
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num_seq_pkts, page_size,
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nbr_of_banks_DRAM,
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nbr_of_banks_util,
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addr_mapping,
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nbr_of_ranks);
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DPRINTF(TrafficGen, "State: %d DramGen\n", id);
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} else {
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// Will rotate to the next rank after rotating
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// through all banks, for each command type.
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// In the 50% read case, series will be issued
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// for both RD & WR before the rank in incremented
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unsigned int max_seq_count_per_rank =
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(read_percent == 50) ? nbr_of_banks_util * 2
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: nbr_of_banks_util;
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states[id] = new DramRotGen(name(), masterID,
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duration, start_addr,
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end_addr, blocksize,
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min_period, max_period,
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read_percent, data_limit,
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num_seq_pkts, page_size,
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nbr_of_banks_DRAM,
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nbr_of_banks_util,
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addr_mapping,
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nbr_of_ranks,
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max_seq_count_per_rank);
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DPRINTF(TrafficGen, "State: %d DramRotGen\n", id);
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}
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}
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} else {
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fatal("%s: Unknown traffic generator mode: %s",
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name(), mode);
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}
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} else if (keyword == "TRANSITION") {
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Transition transition;
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is >> transition.from >> transition.to >> transition.p;
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transitions.push_back(transition);
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DPRINTF(TrafficGen, "Transition: %d -> %d\n", transition.from,
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transition.to);
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} else if (keyword == "INIT") {
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// set the initial state as the active state
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is >> currState;
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init_state_set = true;
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DPRINTF(TrafficGen, "Initial state: %d\n", currState);
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}
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}
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}
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if (!init_state_set)
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fatal("%s: initial state not specified (add 'INIT <id>' line "
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"to the config file)\n", name());
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// resize and populate state transition matrix
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transitionMatrix.resize(states.size());
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for (size_t i = 0; i < states.size(); i++) {
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transitionMatrix[i].resize(states.size());
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}
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for (vector<Transition>::iterator t = transitions.begin();
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t != transitions.end(); ++t) {
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transitionMatrix[t->from][t->to] = t->p;
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}
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// ensure the egress edges do not have a probability larger than
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// one
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for (size_t i = 0; i < states.size(); i++) {
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double sum = 0;
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for (size_t j = 0; j < states.size(); j++) {
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sum += transitionMatrix[i][j];
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}
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// avoid comparing floating point numbers
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if (abs(sum - 1.0) > 0.001)
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fatal("%s has transition probability != 1 for state %d\n",
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name(), i);
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}
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// close input file
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infile.close();
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}
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void
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TrafficGen::transition()
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{
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// exit the current state
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states[currState]->exit();
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// determine next state
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double p = random_mt.random<double>();
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assert(currState < transitionMatrix.size());
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double cumulative = 0.0;
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size_t i = 0;
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do {
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cumulative += transitionMatrix[currState][i];
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++i;
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} while (cumulative < p && i < transitionMatrix[currState].size());
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enterState(i - 1);
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}
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void
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TrafficGen::enterState(uint32_t newState)
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{
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DPRINTF(TrafficGen, "Transition to state %d\n", newState);
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currState = newState;
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// we could have been delayed and not transitioned on the exact
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// tick when we were supposed to (due to back pressure when
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// sending a packet)
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nextTransitionTick = curTick() + states[currState]->duration;
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states[currState]->enter();
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}
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void
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TrafficGen::recvReqRetry()
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{
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assert(retryPkt != NULL);
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DPRINTF(TrafficGen, "Received retry\n");
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numRetries++;
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// attempt to send the packet, and if we are successful start up
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// the machinery again
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if (port.sendTimingReq(retryPkt)) {
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retryPkt = NULL;
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// remember how much delay was incurred due to back-pressure
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// when sending the request, we also use this to derive
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// the tick for the next packet
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Tick delay = curTick() - retryPktTick;
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retryPktTick = 0;
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retryTicks += delay;
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if (drainState() != DrainState::Draining) {
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// packet is sent, so find out when the next one is due
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nextPacketTick = states[currState]->nextPacketTick(elasticReq,
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delay);
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Tick nextEventTick = std::min(nextPacketTick, nextTransitionTick);
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schedule(updateEvent, std::max(curTick(), nextEventTick));
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} else {
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// shut things down
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nextPacketTick = MaxTick;
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nextTransitionTick = MaxTick;
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signalDrainDone();
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}
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}
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}
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void
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TrafficGen::regStats()
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{
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// Initialise all the stats
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using namespace Stats;
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numPackets
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.name(name() + ".numPackets")
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.desc("Number of packets generated");
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numRetries
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.name(name() + ".numRetries")
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.desc("Number of retries");
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retryTicks
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.name(name() + ".retryTicks")
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.desc("Time spent waiting due to back-pressure (ticks)");
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}
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bool
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TrafficGen::TrafficGenPort::recvTimingResp(PacketPtr pkt)
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{
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delete pkt->req;
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delete pkt;
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return true;
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}
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