Andreas Hansson 55cf3f4ac1 MEM: Removing the default port peer from Python ports ... In preparation for the introduction of Master and Slave ports, this patch removes the default port parameter in the Python port and thus forces the argument list of the Port to contain only the description. The drawback at this point is that the config port and dma port of PCI and DMA devices have to be connected explicitly. This is key for future diversification as the pio and config port are slaves, but the dma port is a master.		2012-01-17 12:55:09 -06:00
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Benchmarks.py	ARM: Update config files for Android/BBench images available on website.	2011-12-15 00:43:35 -05:00
CacheConfig.py	configs: cache: add cache line size option	2011-02-23 14:26:55 -05:00
Caches.py	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	2011-12-01 00:15:22 -08:00
cpu2000.py	cpu2000: Add missing art benchmark to all	2012-01-09 18:08:20 -06:00
FSConfig.py	MEM: Removing the default port peer from Python ports	2012-01-17 12:55:09 -06:00
Options.py	Config: Add support for restoring using a timing CPU	2012-01-11 13:50:18 -06:00
Simulation.py	Config: Add support for restoring using a timing CPU	2012-01-11 13:50:18 -06:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00