79613686f0
minor change to syntax of 'def operands' in ISA descriptions.
arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
Change 'def operands' statement to work with new
isa_parser changes.
arch/isa_parser.py:
Merge OperandTraits and OperandDescriptor objects into a
unified hierarchy of Operand objects.
Required a change in the syntax of the 'def operands'
statement in the ISA description.
--HG--
extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
35 lines
1.2 KiB
Text
35 lines
1.2 KiB
Text
def operand_types {{
|
|
'sb' : ('signed int', 8),
|
|
'ub' : ('unsigned int', 8),
|
|
'shw' : ('signed int', 16),
|
|
'uhw' : ('unsigned int', 16),
|
|
'sw' : ('signed int', 32),
|
|
'uw' : ('unsigned int', 32),
|
|
'sdw' : ('signed int', 64),
|
|
'udw' : ('unsigned int', 64),
|
|
'sf' : ('float', 32),
|
|
'df' : ('float', 64),
|
|
'qf' : ('float', 128)
|
|
}};
|
|
|
|
def operands {{
|
|
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
|
|
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
|
|
'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
|
|
|
|
'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
|
|
'Sa': ('IntReg', 'uw', 'SA', 'IsInteger', 4),
|
|
|
|
'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
|
|
'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
|
|
'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
|
|
|
|
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
|
|
|
|
#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
|
|
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
|
|
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
|
|
# The next two are hacks for non-full-system call-pal emulation
|
|
#'R0': ('IntReg', 'uq', '0', None, 1),
|
|
#'R16': ('IntReg', 'uq', '16', None, 1)
|
|
}};
|