gem5/src/mem/cache
Kevin Lim 78de00091b 3 memory system fixes:
1. Update packet's flags properly when a snoop happens
2. Don't allow accesses to read a block's data if the block has outstanding MSHRs.  This avoids a RAW hazard in MP systems that the memory system was not detecting properly earlier (a write required a block to upgrade, and while the upgrade was outstanding, a read came along and read old data).
3. Update MSHR's request upon a response being handled.  If the MSHR has more targets than it can respond to in one cycle, then its request must be properly updated to the new head of the targets list.

src/mem/bus.cc:
    Update packet's flags properly upon snoop.
src/mem/cache/cache_impl.hh:
    Be sure to not allow accesses to a block with outstanding MSHRs.
src/mem/cache/miss/miss_queue.cc:
    Update MSHR's request upon a response being handled.

--HG--
extra : convert_revision : 76a9abc610ca3f1904f075ad21637148a41982d6
2007-03-23 13:09:37 -04:00
..
coherence Remove assertion. It's not needed and messes up writebacks when a 2 level cache is used in a uniprocessor setting. 2006-11-28 11:41:08 -05:00
miss 3 memory system fixes: 2007-03-23 13:09:37 -04:00
prefetch No need to template prefetcher on cache TagStore type. 2006-12-18 21:53:06 -08:00
tags make our code a little more standards compliant 2007-01-26 18:48:51 -05:00
base_cache.cc Split CachePort class into CpuSidePort and MemSidePort 2006-12-13 22:04:36 -08:00
base_cache.hh No need to template prefetcher on cache TagStore type. 2006-12-18 21:53:06 -08:00
cache.cc Get rid of generic CacheTags object (fold back into Cache). 2006-12-18 20:47:12 -08:00
cache.hh Streamline Cache/Tags interface: get rid of redundant functions, 2006-12-18 23:07:52 -08:00
cache_blk.hh First cut at LL/SC support in caches (atomic mode only). 2006-10-19 00:33:33 -07:00
cache_builder.cc No need to template prefetcher on cache TagStore type. 2006-12-18 21:53:06 -08:00
cache_impl.hh 3 memory system fixes: 2007-03-23 13:09:37 -04:00