252 lines
8.3 KiB
C
252 lines
8.3 KiB
C
/*
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* VID: [T1.2] PT: [Fri Apr 21 16:47:18 1995] SF: [platform.h]
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* TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ]
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*/
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#define __PLATFORM_LOADED 1
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/*
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*****************************************************************************
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** *
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** Copyright © 1993, 1994 *
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** by Digital Equipment Corporation, Maynard, Massachusetts. *
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** *
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** All Rights Reserved *
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** *
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** Permission is hereby granted to use, copy, modify and distribute *
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** this software and its documentation, in both source code and *
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** object code form, and without fee, for the purpose of distribution *
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** of this software or modifications of this software within products *
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** incorporating an integrated circuit implementing Digital's AXP *
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** architecture, regardless of the source of such integrated circuit, *
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** provided that the above copyright notice and this permission notice *
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** appear in all copies, and that the name of Digital Equipment *
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** Corporation not be used in advertising or publicity pertaining to *
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** distribution of the document or software without specific, written *
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** prior permission. *
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** *
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** Digital Equipment Corporation disclaims all warranties and/or *
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** guarantees with regard to this software, including all implied *
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** warranties of fitness for a particular purpose and merchantability, *
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** and makes no representations regarding the use of, or the results *
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** of the use of, the software and documentation in terms of correctness, *
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** accuracy, reliability, currentness or otherwise; and you rely on *
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** the software, documentation and results solely at your own risk. *
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** *
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** AXP is a trademark of Digital Equipment Corporation. *
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** *
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*****************************************************************************
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**
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** FACILITY:
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**
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** DECchip 21164 OSF/1 PALcode
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**
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** MODULE:
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**
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** platform.h
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**
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** MODULE DESCRIPTION:
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**
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** Platform specific definitions.
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**
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** AUTHOR: Lance Berc (taken from EB164 code)
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**
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** CREATION DATE: 14-Jun-1995
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**
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** $Id: platform.h,v 1.1.1.1 1997/10/30 23:27:20 verghese Exp $
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**
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** MODIFICATION HISTORY:
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**
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** $Log: platform.h,v $
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** Revision 1.1.1.1 1997/10/30 23:27:20 verghese
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** current 10/29/97
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**
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* Revision 1.1 1995/06/14 18:50:42 berc
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* Initial revision
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*
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*/
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#if !defined(CONSOLE_ENTRY)
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#define CONSOLE_ENTRY 0x10000
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#endif /* CONSOLE_ENTRY */
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#define DEBUGDEATH(c) \
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lda a0, c(zero) ; \
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br DebugDeath
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#define DEBUGSTORE(c) \
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stq_p t0,0(zero) ; \
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stq_p t1,8(zero) ; \
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lda t0, 0x400(zero) ; \
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sll t0, 29, t0 ; \
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ldah t0, 0x280(t0) ; \
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9: lda t1, 0x140(t0) ; \
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ldl_p t1, 0(t1) ; \
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srl t1, 16, t1 ; \
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and t1, 0x20, t1 ; \
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beq t1, 9b ; \
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lda t1, c(zero) ; \
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stl_p t1, 0(t0) ; \
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mb ; \
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ldq_p t1, 8(zero) ; \
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ldq_p t0, 0(zero)
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/*
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** IPL translation table definitions:
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**
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** EB164 specific IRQ pins are
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**
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** Line IPL Source OSF/1 IPL
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** ---- --- ------ ---------
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** IRQ0 20 Corrected ECC error 7
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** IRQ1 21 PCI/ISA 3
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** IRQ2 22 Real Time Clock 5
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** IRQ3 23 SIO NMI, CIA errors 7
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**
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** The mask contains one byte for each IPL level, with IPL0 in the
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** least significant (right-most) byte and IPL7 in the most
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** significant (left-most) byte. Each byte in the mask maps the
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** OSF/1 IPL to the DC21164 IPL.
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**
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** OSF/1 IPL IPL
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** --------- ---
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** 0 0
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** 1 1
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** 2 2
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** 3 21 (to account for PCI/ISA at IPL 21)
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** 4 21
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** 5 22 (to account for clock at IPL 21)
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** 6 30 (to account for powerfail)
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** 7 31
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*/
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#define INT_K_MASK_HIGH 0x1F1E1615
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#define INT_K_MASK_LOW 0x15020100
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#define BYTE_ENABLE_SHIFT 5
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/*
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** Dallas DS1287A Real-Time Clock (RTC) Definitions:
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*/
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#define RTCADD 0x160000
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#define RTCDAT 0x170000
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/*
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** Serial Port (COM) Definitions:
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*/
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#define DLA_K_BRG 12 /* Baud Rate Divisor = 9600 */
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#define LSR_V_THRE 5 /* Xmit Holding Register Empty Bit */
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#define LCR_M_WLS 3 /* Word Length Select Mask */
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#define LCR_M_STB 4 /* Number Of Stop Bits Mask */
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#define LCR_M_PEN 8 /* Parity Enable Mask */
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#define LCR_M_DLAB 128 /* Divisor Latch Access Bit Mask */
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#define LCR_K_INIT (LCR_M_WLS | LCR_M_STB)
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#define MCR_M_DTR 1 /* Data Terminal Ready Mask */
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#define MCR_M_RTS 2 /* Request To Send Mask */
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#define MCR_M_OUT1 4 /* Output 1 Control Mask */
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#define MCR_M_OUT2 8 /* UART Interrupt Mask Enable */
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#define MCR_K_INIT (MCR_M_DTR | \
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MCR_M_RTS | \
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MCR_M_OUT1 | \
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MCR_M_OUT2)
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/* CPU Adr[39:29]=0x500 select PCI Mem. */
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#define PCI_MEM 0x400
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#define SLOT_D_COM1 (0x140000)
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#define SLOT_D_COM2 (0x150000)
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#define COM1_RBR (SLOT_D_COM1 | (0x0 << 1)) /* Receive Buffer Register Offset */
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#define COM1_THR (SLOT_D_COM1 | (0x0 << 1)) /* Xmit Holding Register Offset */
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#define COM1_IER (SLOT_D_COM1 | (0x1 << 1)) /* Interrupt Enable Register Offset */
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#define COM1_IIR (SLOT_D_COM1 | (0x2 << 1)) /* Interrupt ID Register Offset */
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#define COM1_LCR (SLOT_D_COM1 | (0x3 << 1)) /* Line Control Register Offset */
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#define COM1_MCR (SLOT_D_COM1 | (0x4 << 1)) /* Modem Control Register Offset */
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#define COM1_LSR (SLOT_D_COM1 | (0x5 << 1)) /* Line Status Register Offset */
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#define COM1_MSR (SLOT_D_COM1 | (0x6 << 1)) /* Modem Status Register Offset */
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#define COM1_SCR (SLOT_D_COM1 | (0x7 << 1)) /* Scratch Register Offset */
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#define COM1_DLL (SLOT_D_COM1 | (0x8 << 1)) /* Divisor Latch (LS) Offset */
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#define COM1_DLH (SLOT_D_COM1 | (0x9 << 1)) /* Divisor Latch (MS) Offset */
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#define COM2_RBR (SLOT_D_COM2 | (0x0 << 1))
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#define COM2_THR (SLOT_D_COM2 | (0x0 << 1))
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#define COM2_IER (SLOT_D_COM2 | (0x1 << 1))
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#define COM2_IIR (SLOT_D_COM2 | (0x2 << 1))
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#define COM2_LCR (SLOT_D_COM2 | (0x3 << 1))
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#define COM2_MCR (SLOT_D_COM2 | (0x4 << 1))
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#define COM2_LSR (SLOT_D_COM2 | (0x5 << 1))
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#define COM2_MSR (SLOT_D_COM2 | (0x6 << 1))
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#define COM2_SCR (SLOT_D_COM2 | (0x7 << 1))
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#define COM2_DLL (SLOT_D_COM2 | (0x8 << 1))
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#define COM2_DLH (SLOT_D_COM2 | (0x9 << 1))
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/*
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** Macro to define a port address
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*/
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#define IO_MASK 0x7FFFFFF
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/* NOTE ON ADDITIONAL PORT DEFINITION:
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**
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** We also need to set bit 39! Since the span between bit 39
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** and the byte enable field is more than 32, we set bit 39 in the
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** port macros.
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*/
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/*
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** Macro to write a byte literal to a specified port
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*/
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#define OutPortByte(port,val,tmp0,tmp1) \
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LDLI (tmp0, port); \
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sll tmp0, BYTE_ENABLE_SHIFT, tmp0; \
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lda tmp1, PCI_MEM(zero); \
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sll tmp1, 29, tmp1; \
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bis tmp0, tmp1, tmp0; \
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lda tmp1, (val)(zero); \
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sll tmp1, 8*(port & 3), tmp1; \
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stl_p tmp1, 0x00(tmp0); \
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mb
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/*
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** Macro to write a byte from a register to a specified port
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*/
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#define OutPortByteReg(port,reg,tmp0,tmp1) \
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LDLI (tmp0, port); \
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sll tmp0, BYTE_ENABLE_SHIFT, tmp0; \
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lda tmp1, PCI_MEM(zero); \
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sll tmp1, 29, tmp1; \
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bis tmp0, tmp1, tmp0; \
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sll reg, 8*(port & 3), tmp1; \
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stl_p tmp1, 0x00(tmp0); \
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mb
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/*
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** Macro to write a longword from a register to a specified port
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*/
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#define OutPortLongReg(port,reg,tmp0,tmp1) \
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LDLI (tmp0, port); \
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sll tmp0, BYTE_ENABLE_SHIFT, tmp0; \
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lda tmp1, PCI_MEM(zero); \
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sll tmp1, 29, tmp1; \
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bis tmp0, tmp1, tmp0; \
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stl_p tmp1, 0x18(tmp0); \
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mb
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/*
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** Macro to read a byte from a specified port
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*/
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#define InPortByte(port,tmp0,tmp1) \
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LDLI (tmp0, port); \
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sll tmp0, BYTE_ENABLE_SHIFT, tmp0; \
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lda tmp1, PCI_MEM(zero); \
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sll tmp1, 29, tmp1; \
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bis tmp0, tmp1, tmp0; \
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ldl_p tmp0, 0x00(tmp0); \
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srl tmp0, (8 * (port & 3)), tmp0; \
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zap tmp0, 0xfe, tmp0
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