d7fba9784e
Most of the changes were to fix broken macros in platfrom_tlaser.s
palcode/Makefile:
Completly new makefile to build palcode
palcode/ev5_alpha_defs.h:
fixed a broken define
palcode/ev5_impure.h:
macro fixes
palcode/platform_srcmax.s:
manual macro expansion of broken macros... this file isn't needed to
build tlaser palcode
palcode/platform_tlaser.s:
lots of fixups to make the code assemble
424 lines
13 KiB
C
424 lines
13 KiB
C
#ifndef EV5_IMPURE_INCLUDED
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#define EV5_IMPURE_INCLUDED
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/*
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// This uses the Hudson file format from "impure.h" but with the fields from
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// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95
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//orig file: impure.sdl
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//orig
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//orig Abstract: PAL impure scratch area and logout area data structure definitions for
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//orig Alpha firmware.
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//orig
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//orig
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//orig module $pal_impure;
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//orig
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//orig Edit Date Who Description
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//orig ---- --------- --- ---------------------
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//orig 1 7-Jul-93 JEM Initial Entry
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//orig 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area
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//orig Delete mvptbr
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//orig Calculate pal$logout from end of impure area
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//orig 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions
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//orig 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, pmctr_ctl;
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//orig add ic_perr_stat, pmctr, dc_perr_stat, sc_stat, sc_addr, sc_ctl,
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//orig bc_tag_addr, ei_stat, ei_addr, fill_syn, ld_lock
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//orig 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be consistent with ev4
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//orig add cns$ipr_offset
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//orig 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again.
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//orig 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant to mchk logout frame
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//orig
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//orig
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//orig constant REVISION equals 7 prefix IMPURE$; // Revision number of this file
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//orig
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** Macros for saving/restoring data to/from the PAL impure scratch
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** area.
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**
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** The console save state area is larger than the addressibility
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** of the HW_LD/ST instructions (10-bit signed byte displacement),
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** so some adjustments to the base offsets, as well as the offsets
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** within each base region, are necessary.
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**
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** The console save state area is divided into two segments; the
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** CPU-specific segment and the platform-specific segment. The
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** state that is saved in the CPU-specific segment includes GPRs,
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** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved
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** in the platform-specific segment.
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**
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** The impure pointer will need to be adjusted by a different offset
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** value for each region within a given segment. The SAVE and RESTORE
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** macros will auto-magically adjust the offsets accordingly.
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**
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*/
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#if 0
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#define SAVE_GPR(reg,offset,base) \
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stq_p reg, ((offset-0x200)&0x3FF)(base)
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#define RESTORE_GPR(reg,offset,base) \
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ldq_p reg, ((offset-0x200)&0x3FF)(base)
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#define SAVE_FPR(reg,offset,base) \
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stt reg, ((offset-0x200)&0x3FF)(base)
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#define RESTORE_FPR(reg,offset,base) \
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ldt reg, ((offset-0x200)&0x3FF)(base)
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#define SAVE_IPR(reg,offset,base) \
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mfpr v0, reg; \
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stq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base)
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#define RESTORE_IPR(reg,offset,base) \
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ldq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base); \
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mtpr v0, reg
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#define SAVE_SHADOW(reg,offset,base) \
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stq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base)
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#define RESTORE_SHADOW(reg,offset,base)\
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ldq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base)
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#else
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//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X))
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#define SEXT10(X) ((X) & 0x3ff)
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//#define SEXT10(X) (((X) << 55) >> 55)
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#define SAVE_GPR(reg,offset,base) \
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stq_p reg, (SEXT10(offset-0x200))(base)
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#define RESTORE_GPR(reg,offset,base) \
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ldq_p reg, (SEXT10(offset-0x200))(base)
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#define SAVE_FPR(reg,offset,base) \
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stt reg, (SEXT10(offset-0x200))(base)
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#define RESTORE_FPR(reg,offset,base) \
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ldt reg, (SEXT10(offset-0x200))(base)
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#define SAVE_IPR(reg,offset,base) \
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mfpr v0, reg; \
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stq_p v0, (SEXT10(offset-CNS_Q_IPR))(base)
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#define RESTORE_IPR(reg,offset,base) \
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ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \
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mtpr v0, reg
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#define SAVE_SHADOW(reg,offset,base) \
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stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base)
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#define RESTORE_SHADOW(reg,offset,base)\
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ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base)
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#endif
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/* orig Structure of the processor-specific impure area */
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/* orig aggregate impure struct prefix "" tag "";
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* orig cns$flag quadword;
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* orig cns$hlt quadword;
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*/
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/* Define base for debug monitor compatibility */
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#define CNS_Q_BASE 0x000
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#define CNS_Q_FLAG 0x100
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#define CNS_Q_HALT 0x108
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/* orig constant (
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* orig cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7,
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* orig cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15,
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* orig cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23,
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* orig cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31
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* orig ) equals . increment 8 prefix "" tag "";
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* orig cns$gpr quadword dimension 32;
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*/
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/* Offset to base of saved GPR area - 32 quadword */
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#define CNS_Q_GPR 0x110
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#define cns_gpr CNS_Q_GPR
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/* orig constant (
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* orig cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7,
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* orig cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15,
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* orig cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23,
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* orig cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31
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* orig ) equals . increment 8 prefix "" tag "";
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* orig cns$fpr quadword dimension 32;
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*/
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/* Offset to base of saved FPR area - 32 quadwords */
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#define CNS_Q_FPR 0x210
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/* orig #t=.;
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* orig cns$mchkflag quadword;
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*/
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#define CNS_Q_MCHK 0x310
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/* orig constant cns$pt_offset equals .;
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* orig constant (
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* orig cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6,
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* orig cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13,
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* orig cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20,
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* orig cns$pt21,cns$pt22,cns$pt23
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* orig ) equals . increment 8 prefix "" tag "";
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* orig cns$pt quadword dimension 24;
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*/
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/* Offset to base of saved PALtemp area - 25 quadwords */
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#define CNS_Q_PT 0x318
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/* orig cns$shadow8 quadword;
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* orig cns$shadow9 quadword;
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* orig cns$shadow10 quadword;
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* orig cns$shadow11 quadword;
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* orig cns$shadow12 quadword;
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* orig cns$shadow13 quadword;
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* orig cns$shadow14 quadword;
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* orig cns$shadow25 quadword;
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*/
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/* Offset to base of saved PALshadow area - 8 quadwords */
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#define CNS_Q_SHADOW 0x3D8
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/* Offset to base of saved IPR area */
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#define CNS_Q_IPR 0x418
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/* orig constant cns$ipr_offset equals .; */
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/* orig cns$exc_addr quadword; */
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#define CNS_Q_EXC_ADDR 0x418
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/* orig cns$pal_base quadword; */
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#define CNS_Q_PAL_BASE 0x420
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/* orig cns$mm_stat quadword; */
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#define CNS_Q_MM_STAT 0x428
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/* orig cns$va quadword; */
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#define CNS_Q_VA 0x430
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/* orig cns$icsr quadword; */
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#define CNS_Q_ICSR 0x438
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/* orig cns$ipl quadword; */
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#define CNS_Q_IPL 0x440
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/* orig cns$ps quadword; // Ibox current mode */
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#define CNS_Q_IPS 0x448
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/* orig cns$itb_asn quadword; */
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#define CNS_Q_ITB_ASN 0x450
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/* orig cns$aster quadword; */
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#define CNS_Q_ASTER 0x458
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/* orig cns$astrr quadword; */
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#define CNS_Q_ASTRR 0x460
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/* orig cns$isr quadword; */
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#define CNS_Q_ISR 0x468
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/* orig cns$ivptbr quadword; */
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#define CNS_Q_IVPTBR 0x470
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/* orig cns$mcsr quadword; */
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#define CNS_Q_MCSR 0x478
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/* orig cns$dc_mode quadword; */
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#define CNS_Q_DC_MODE 0x480
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/* orig cns$maf_mode quadword; */
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#define CNS_Q_MAF_MODE 0x488
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/* orig cns$sirr quadword; */
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#define CNS_Q_SIRR 0x490
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/* orig cns$fpcsr quadword; */
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#define CNS_Q_FPCSR 0x498
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/* orig cns$icperr_stat quadword; */
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#define CNS_Q_ICPERR_STAT 0x4A0
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/* orig cns$pmctr quadword; */
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#define CNS_Q_PM_CTR 0x4A8
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/* orig cns$exc_sum quadword; */
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#define CNS_Q_EXC_SUM 0x4B0
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/* orig cns$exc_mask quadword; */
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#define CNS_Q_EXC_MASK 0x4B8
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/* orig cns$intid quadword; */
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#define CNS_Q_INT_ID 0x4C0
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/* orig cns$dcperr_stat quadword; */
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#define CNS_Q_DCPERR_STAT 0x4C8
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/* orig cns$sc_stat quadword; */
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#define CNS_Q_SC_STAT 0x4D0
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/* orig cns$sc_addr quadword; */
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#define CNS_Q_SC_ADDR 0x4D8
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/* orig cns$sc_ctl quadword; */
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#define CNS_Q_SC_CTL 0x4E0
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/* orig cns$bc_tag_addr quadword; */
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#define CNS_Q_BC_TAG_ADDR 0x4E8
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/* orig cns$ei_stat quadword; */
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#define CNS_Q_EI_STAT 0x4F0
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/* orig cns$ei_addr quadword; */
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#define CNS_Q_EI_ADDR 0x4F8
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/* orig cns$fill_syn quadword; */
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#define CNS_Q_FILL_SYN 0x500
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/* orig cns$ld_lock quadword; */
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#define CNS_Q_LD_LOCK 0x508
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/* orig cns$bc_ctl quadword; // shadow of on chip bc_ctl */
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#define CNS_Q_BC_CTL 0x510
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/* orig cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */
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#define CNS_Q_PM_CTL 0x518
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/* orig cns$bc_config quadword; // shadow of on chip bc_config */
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#define CNS_Q_BC_CFG 0x520
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/* orig constant cns$size equals .;
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* orig
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* orig constant pal$impure_common_size equals (%x0200 +7) & %xfff8;
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* orig constant pal$impure_specific_size equals (.+7) & %xfff8;
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* orig constant cns$mchksize equals (.+7-#t) & %xfff8;
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* orig constant pal$logout_area equals pal$impure_specific_size ;
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* orig end impure;
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*/
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/* This next set of stuff came from the old code ..pb */
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#define CNS_Q_SROM_REV 0x528
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#define CNS_Q_PROC_ID 0x530
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#define CNS_Q_MEM_SIZE 0x538
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#define CNS_Q_CYCLE_CNT 0x540
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#define CNS_Q_SIGNATURE 0x548
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#define CNS_Q_PROC_MASK 0x550
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#define CNS_Q_SYSCTX 0x558
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#define MACHINE_CHECK_CRD_BASE 0
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#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8)
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/* orig
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* orig aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$;
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* orig SPROCESS bitfield length 1 ;
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* orig FILL_0 bitfield length 3 fill tag $$;
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* orig FRQ2 bitfield length 2 ;
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* orig FRQ1 bitfield length 2 ;
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* orig FRQ0 bitfield length 2 ;
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* orig CTL2 bitfield length 2 ;
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* orig CTL1 bitfield length 2 ;
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* orig CTL0 bitfield length 2 ;
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* orig FILL_1 bitfield length 16 fill tag $$;
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* orig FILL_2 bitfield length 32 fill tag $$;
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* orig end EV5PMCTRCTL_BITS;
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* orig
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* orig end_module $pal_impure;
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* orig
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* orig module $pal_logout;
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* orig
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* orig //
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* orig // Start definition of Corrected Error Frame
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* orig //
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*/
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/*
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* orig aggregate crd_logout struct prefix "" tag "";
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*/
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#ifdef SIMOS
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#define pal_logout_area 0x600
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#define mchk_crd_base 0
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#endif
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/* orig mchk$crd_flag quadword; */
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#define mchk_crd_flag 0
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/* orig mchk$crd_offsets quadword; */
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#define mchk_crd_offsets 8
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/* orig
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* orig // Pal-specific information */
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#define mchk_crd_mchk_code 0x10
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/* orig mchk$crd_mchk_code quadword;
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* orig
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* orig // CPU-specific information
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* orig constant mchk$crd_cpu_base equals . ;
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* orig mchk$crd_ei_addr quadword; */
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#define mchk_crd_ei_addr 0x18
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/* orig mchk$crd_fill_syn quadword; */
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#define mchk_crd_fill_syn 0x20
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/* orig mchk$crd_ei_stat quadword; */
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#define mchk_crd_ei_stat 0x28
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/* orig mchk$crd_isr quadword; */
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#define mchk_crd_isr 0x30
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/*
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* Hacked up constants for the turbolaser build. Hope
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* this is moreless correct
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*/
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#define mchk_crd_whami 0x38
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#define mchk_crd_tldev 0x40
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#define mchk_crd_tlber 0x48
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#define mchk_crd_tlesr0 0x50
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#define mchk_crd_tlesr1 0x58
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#define mchk_crd_tlesr2 0x60
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#define mchk_crd_tlesr3 0x68
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#define mchk_crd_rsvd 0x70
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#ifdef SIMOS
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/*
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* mchk area seems different for tlaser
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*/
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#define mchk_crd_size 0x80
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#define mchk_mchk_base (mchk_crd_size)
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#define mchk_tlber 0x0
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#define mchk_tlepaerr 0x8
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#define mchk_tlepderr 0x10
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#define mchk_tlepmerr 0x18
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#endif
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/* orig
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* orig // System-specific information
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* orig constant mchk$crd_sys_base equals . ;
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* orig constant mchk$crd_size equals (.+7) & %xfff8;
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* orig
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* orig end crd_logout;
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* orig //
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* orig // Start definition of Machine check logout Frame
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* orig //
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* orig aggregate logout struct prefix "" tag "";
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* orig mchk$flag quadword; */
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/* orig mchk$offsets quadword; */
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/* orig
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* orig // Pal-specific information
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* orig mchk$mchk_code quadword; */
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/*
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* orig mchk$pt quadword dimension 24;
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* orig
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* orig // CPU-specific information
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* orig constant mchk$cpu_base equals . ;
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* orig mchk$exc_addr quadword;
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* orig mchk$exc_sum quadword;
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* orig mchk$exc_mask quadword;
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* orig mchk$pal_base quadword;
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* orig mchk$isr quadword;
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* orig mchk$icsr quadword;
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* orig mchk$ic_perr_stat quadword;
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* orig mchk$dc_perr_stat quadword;
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* orig mchk$va quadword;
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* orig mchk$mm_stat quadword;
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* orig mchk$sc_addr quadword;
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* orig mchk$sc_stat quadword;
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* orig mchk$bc_tag_addr quadword;
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* orig mchk$ei_addr quadword;
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* orig mchk$fill_syn quadword;
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* orig mchk$ei_stat quadword;
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* orig mchk$ld_lock quadword;
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* orig
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* orig // System-specific information
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* orig
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* orig constant mchk$sys_base equals . ;
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* orig mchk$sys_ipr1 quadword ; // Holder for system-specific stuff
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* orig
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* orig constant mchk$size equals (.+7) & %xfff8;
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* orig
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* orig
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* orig constant mchk$crd_base equals 0 ;
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* orig constant mchk$mchk_base equals mchk$crd_size ;
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* orig
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* orig
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* orig end logout;
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* orig
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* orig end_module $pal_logout;
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*/
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/* this is lingering in the old ladbx code but looks like it was from ev4 days.
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* This was 0x160 in the old days..pb
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*/
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#define LAF_K_SIZE MACHINE_CHECK_SIZE
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#endif
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