381 lines
13 KiB
C
381 lines
13 KiB
C
#ifndef __AM79C960_H_LOADED
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#define __AM79C960_H_LOADED
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/*****************************************************************************
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Copyright © 1993, 1994 Digital Equipment Corporation,
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Maynard, Massachusetts.
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All Rights Reserved
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Permission to use, copy, modify, and distribute this software and its
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documentation for any purpose and without fee is hereby granted, provided
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that the copyright notice and this permission notice appear in all copies
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of software and supporting documentation, and that the name of Digital not
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be used in advertising or publicity pertaining to distribution of the software
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without specific, written prior permission. Digital grants this permission
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provided that you prominently mark, as not part of the original, any
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modifications made to this software or documentation.
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Digital Equipment Corporation disclaims all warranties and/or guarantees
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with regard to this software, including all implied warranties of fitness for
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a particular purpose and merchantability, and makes no representations
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regarding the use of, or the results of the use of, the software and
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documentation in terms of correctness, accuracy, reliability, currentness or
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otherwise; and you rely on the software, documentation and results solely at
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your own risk.
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******************************************************************************/
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/*
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* $Id: am79c960.h,v 1.1.1.1 1997/10/30 23:27:13 verghese Exp $
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*/
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/*
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* MODULE DESCRIPTION:
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*
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* Parameters and logicals for AM79C960 drivers in EB64 monitor
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*
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* HISTORY:
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*
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* $Log: am79c960.h,v $
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* Revision 1.1.1.1 1997/10/30 23:27:13 verghese
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* current 10/29/97
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*
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* Revision 1.8 1994/12/12 21:31:59 cruz
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* Fixed bug in TMD3 constants
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*
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* Revision 1.7 1994/08/05 20:13:47 fdh
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* Updated Copyright header and RCS $Id: identifier.
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*
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* Revision 1.6 1994/06/28 20:08:21 fdh
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* Modified filenames and build precedure to fit into a FAT filesystem.
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*
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* Revision 1.5 1994/06/24 15:26:49 rusling
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* Fixed initialization alignment problems.
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*
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* Revision 1.4 1994/06/20 14:18:59 fdh
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* Fixup header file preprocessor #include conditionals.
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*
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* Revision 1.3 1994/06/17 19:34:01 fdh
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* Clean-up...
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*
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* Revision 1.2 1994/06/03 20:11:11 fdh
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* Replaced shorts declared in bitfields to ints.
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*
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* Revision 1.1 1993/08/06 10:10:05 berent
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* Initial revision
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*
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*
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*/
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/* The embedded Ethernet controller on the EB64 is an AMD Am79C960 device.
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*
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* This device integrates an Am7990 LANCE Ethernet controller with an ISA
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* bus interface plus all the serial interface logic bar some discrete
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* termination and isolation transformers for AUI (10base5) and twisted
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* pair (10baseT) connections.
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*
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* The AUI port on EB64 is connected to an Am7996 thinwire transceiver to
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* provide a 10base2 port (BNC) as well as the twisted pair (MMJ)
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* connectivity.
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*
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* The device is programmed in a similar but not identical fashion to the
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* LANCE. The following programming differences and features are noted:
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*
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* A RAP/RDP mechanism is used for register access like the LANCE, but with
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* a much larger register set:
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*
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* Initialisation block now part of on-chip register set with new
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* ...features added to the mode register. This can be set up in
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* ...memory and copied by the device using the csr0_INIT bit, or
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* ...programmed directly to the device using the extended CSR map.
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*
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* CSR3 completely changed - interrupt mask and enabling bits for
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* ...new features
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*
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* CSR3 can be accessed while the "LANCE" running
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*
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* A register added for controlling the ISA bus DMA profile eg. FIFO
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* ...watermarks for DMA loads and stores, TX transmission start
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* ...point wrt data in TX FIFO, DMA burstsizes.
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*
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* Registers to overrule ring sizes in initialisation blocks allowing
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* ...ring sizes from 1-64k entries. CSR76 for RX; CSR78 for TX
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*
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* Timer and ID registers
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*
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* Missed pkt and RX collision counters
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*
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* A similar RAP/IDP mechanism is used to program ISA DMA signal timing, ISA
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* bus configuration, bits, and the functionality for the three LED drives
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* provided.
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*
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* The Am79C960 *must* use a 16-bit DMA path, but can use an 8-bit path for
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* CSR (IO) access. It also supports access to a sixteen byte area for
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* keeping the MAC address in PROM. This is always byte-wide access, as is a
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* shared memory mode to a larger local address space, not used on EB64.
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*
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* EB64 accesses to the 79C960 are through the VL82C486 ISA controller. All
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* CSR accesses should be done as 16-bit words, with the VL82C486 taking care
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* of the packing/unpacking issue. Enet PROM accesses are done as byte
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* accesses. The EB64 memory controller will perform read_modify_write cycles
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* into main memory to correctly merge the bytes/words, and preserve longword
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* parity.
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*
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*
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* Please see the Am7990 and Am79C960 literature for definitive lists and
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* further detail.
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*
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* PLEASE NOTE: LANCE is used in many definitions for historical reasons.
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*/
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/* Maximum number of AMD79C960's supported in the EB64 monitor */
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#define AM79C960_MAX_DEVICES 2
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/* Base addresses supported for 79C960 in ISA address space */
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#define EMBEDDED_79C960_BASE 0x360 /* IOAM pins = 0b11 */
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#define OPTION_79C960_BASE 0x300 /* IOAM pins = 0b00 */
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/* Assigned interrupt numbers for 8259 controller */
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#define EMBEDDED_79C960_INT 9
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#define OPTION_79C960_INT 12
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/* Assigned mask numbers for enabling appropriate DMA channel */
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#define EMBEDDED_79C960_DMA 1
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#define OPTION_79C960_DMA 2
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/* CSR access offsets for 79C960 */
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#define HW_ADDR_OFFSET 0 /* The hardware address is at the base address for the device */
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#define RDP_OFFSET 0x10
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#define RAP_OFFSET 0x12
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#define RESET_OFFSET 0x14
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#define IDP_OFFSET 0x16
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#define VSW_OFFSET 0x18
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#define LANCE_CSR0 0 /* Main csr */
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#define LANCE_IADRL 1 /* Init block low address bits */
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#define LANCE_IADRH 2 /* Init block high address bits */
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#define LANCE_CSR3 3 /* Mask and function bits */
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#define LANCE_CSR4 4 /* Additional mask and function bits, only exists on amd 79c960 */
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/* CSR bit definitions - CSR1 and 2 have no bit fields */
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/* CSR0 Bit definitions */
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#define csr0_INIT 0x0001 /* Initialize - can be set with STRT on 79C960*/
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#define csr0_STRT 0x0002 /* Start operation */
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#define csr0_STOP 0x0004 /* Stop LANCE */
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#define csr0_TDMD 0x0008 /* Transmit demand */
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#define csr0_TXON 0x0010 /* Transmitter ON */
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#define csr0_RXON 0x0020 /* Receiver ON */
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#define csr0_IENA 0x0040 /* Interrupt enable */
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#define csr0_INTR 0x0080 /* Interrupt received */
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#define csr0_IDON 0x0100 /* Initialization done */
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#define csr0_TINT 0x0200 /* Transmitter interrupt */
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#define csr0_RINT 0x0400 /* Receiver interrupt */
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#define csr0_MERR 0x0800 /* Memory error */
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#define csr0_MISS 0x1000 /* Missed packet */
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#define csr0_CERR 0x2000 /* Collision error */
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#define csr0_BABL 0x4000 /* Babbling on the wire */
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#define csr0_ERR 0x8000 /* Error logical OR */
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/* CSR3 Bit definitions - all undefined bits reserved */
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#define csr3_EMBA 0x0008 /* Enable Alternate Backoff Algorithm - 79C960 */
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#define csr3_DXMT2PD 0x0010 /* Disable 2-part TX deferral - 79C960 */
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#define csr3_IDONM 0x0100 /* Initialise Done interrupt mask */
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#define csr3_TINT 0x0200 /* TX interrupt mask */
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#define csr3_RINT 0x0400 /* RX interrupt mask */
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#define csr3_MERM 0x0800 /* Memory error interrupt mask */
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#define csr3_MISSM 0x1000 /* Missed pkt interrupt mask */
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#define csr3_BABLM 0x4000 /* Babble interrupt mask */
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#define csr3_MASKALL 0x5F00 /* Mask all CSR3 maskable interrupts */
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/* CSR4 Bit definitions - all undefined bits reserved */
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/* This register is unique to the 79C960 */
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#define csr4_JABM 0x0001 /* Jabber interrupt mask
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#define csr4_JAB 0x0002 /* set if T-MAU detects a jabber condition
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#define csr4_TXSTRTM 0x0004 /* TX start (of packet) interrupt mask */
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#define csr4_TXSTRT 0x0008 /* */
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#define csr4_RCVCCOM 0x0010 /* RX Collision Counter Overflow interrupt mask */
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#define csr4_RCVCCO 0x0020 /* RX Collision Counter Overflow bit */
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#define csr4_MPCOM 0x0100 /* Missed Pkt counter overflow interrupt mask */
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#define csr4_MPCO 0x0200 /* Missed Pkt counter overflow bit */
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#define csr4_ASTRPRCV 0x0400 /* Enable Automatic Pad Stripping on RX - IEEE802.3 */
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#define csr4_APADXMT 0x0800 /* Enable Automatic Padding on TX - IEEE802.3 */
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#define csr4_DPOLL 0x1000 /* Disable polling - TX rings */
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#define csr4_TIMER 0x2000 /* */
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#define csr4_DMAPLUS 0x4000 /* Disable CSR80 DMA burst counter */
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#define csr4_ENTST 0x8000 /* Enable Test mode */
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/* Receive Message Descriptor */
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/* RMD0, RMD2 and RMD3 have no bit fields */
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/* Bits 0 -> 7 of RMD1 part of buffer address */
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#define rmd1_ENP 0x0100 /* End of packet */
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#define rmd1_STP 0x0200 /* Start of packet */
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#define rmd1_BUFF 0x0400 /* Buffer error */
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#define rmd1_CRC 0x0800 /* CRC error */
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#define rmd1_OFLO 0x1000 /* Overflow error */
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#define rmd1_FRAM 0x2000 /* Framing error */
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#define rmd1_ERR 0x4000 /* Error logical OR */
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#define rmd1_OWN 0x8000 /* Who owns it */
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/* Transmit Message Descriptor */
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/* TMD0 and TMD2 have no bit fields */
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/* Bits 0 -> 7 of TMD1 part of buffer address */
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#define tmd1_ENP 0x0100 /* End of packet */
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#define tmd1_STP 0x0200 /* Start of packet */
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#define tmd1_DEF 0x0400 /* Had to defer */
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#define tmd1_ONE 0x0800 /* One eretry needed */
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#define tdm1_MORE 0x1000 /* More than one retry */
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#define tmd1_ADDFCS 0x2000 /* Am79C960 specific - add FCS on pkt basis */
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#define tmd1_ERR 0x4000 /* Error logical OR */
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#define tmd1_OWN 0x8000 /* Who owns it */
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/* Bits 0 -> 9 of TMD3 provide a TDR counter for finding cable faults */
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#define tmd3_RTRY 0x0400 /* Too many retries */
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#define tmd3_LCAR 0x0800 /* Loss of Carrier */
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#define tmd3_LCOL 0x1000 /* Late Collision on send */
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#define tmd3_RES 0x2000 /* RESERVED */
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#define tmd3_UFLO 0x4000 /* Underflow Error */
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#define tmd3_BUFF 0x8000 /* Buffer Error */
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/* For init block - operating modes */
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#define mode_DRX 0x0001 /* Disable receiver */
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#define mode_DTX 0x0002 /* Disable transmitter */
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#define mode_LOOP 0x0004 /* Loopback mode */
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#define mode_DTCR 0x0008 /* Disable transmit CRC */
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#define mode_COLL 0x0010 /* Force collision */
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#define mode_DRTY 0x0020 /* Disable retries */
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#define mode_INTL 0x0040 /* Internal loopback */
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#define mode_PORTSEL0 0x0080 /* 0 = AUI; 1 = T-MAU */
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#define mode_PORTSEL1 0x0100 /* MBZ */
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#define mode_LRT_TSEL 0x0200 /* Low RX threshold/TX mode select */
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#define mode_MENDECL 0x0400 /* MENDEC loopback mode */
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#define mode_DAPC 0x0800 /* T-MAU: disable automatic polarity correction */
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#define mode_DLNKTST 0x1000 /* Disable link status */
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#define mode_DRCVPA 0x2000 /* Disable RX physical address */
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#define mode_DRCVBC 0x4000 /* Disable RX broadcast */
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#define mode_PROM 0x8000 /* Promiscuous mode */
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/* Initialization block. */
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#define LANCE_INIT_BLOCK_SIZE 24
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#define LANCE_INIT_BLOCK_MODE_OFFSET 0
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#define LANCE_INIT_BLOCK_PADR_OFFSET 2
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#define LANCE_INIT_BLOCK_LADRF_OFFSET 8
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#define LANCE_INIT_BLOCK_RD_OFFSET 16
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#define LANCE_INIT_BLOCK_TD_OFFSET 20
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typedef struct {
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unsigned
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radr : 24, /* Ring address. */
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: 5,
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rlen : 3; /* Entries (0=1, 1=2, 2=4, 3=8...) */
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} INIT_BLOCK_DESC;
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/* Receive buffer descriptor. */
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typedef struct{
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unsigned int
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ladr : 24, /* Buffer address. */
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enp : 1, /* End of packet. */
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stp : 1, /* Start of packet. */
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buff : 1, /* Buffer error. */
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crc : 1, /* CRC error. */
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oflo : 1, /* Overflow error. */
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fram : 1, /* Framing error. */
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err : 1, /* Error summary: buff + crc + oflo + fram */
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own : 1; /* Buffer owner: host=0, lance=1. */
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uw bcnt; /* Buffer size. */
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uw mcnt; /* Message size. */
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} LANCE_RECV_BD;
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/* Transmit buffer descriptor. */
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typedef struct{
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unsigned int
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ladr : 24, /* Buffer address. */
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enp : 1, /* End of packet. */
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stp : 1, /* Start of packet. */
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def : 1, /* Deferred. */
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one : 1, /* One retry. */
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more : 1, /* More retries. */
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add_fcs : 1, /* Add FCS on packet basis - 79C960 specific feature */
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err : 1, /* Error summary: lcol + lcar + uflo + rtry */
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own : 1; /* Buffer owner: host=0, lance=1. */
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uw bcnt; /* Buffer size. */
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uw tmd3; /* TMD 3 */
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} LANCE_SEND_BD;
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#define LANCE_OWNS 1
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#define HOST_OWNS 0
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/* Lance counters. */
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typedef struct{
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time_t zeroed;
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int b_recv;
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int b_sent;
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int f_recv;
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int f_sent;
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int mc_b_recv;
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int mc_f_recv;
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int f_sent_def;
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int f_sent_sgl_col;
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int f_sent_mult_col;
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int send_fail_exs_col;
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int send_fail_cc;
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int send_fail_short;
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int send_fail_open;
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int send_fail_flen;
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int send_fail_defer;
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int recv_fail_fcs;
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int recv_fail_f_err;
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int recv_fail_flen;
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int data_overrun;
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int sbuf_unav;
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int ubuf_unav;
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int cc_fail;
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} LANCE_CTRS;
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typedef struct{
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int base_addr;
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int interrupt_line;
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int dma_mask;
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} AM79C960_CONFIG;
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#define AM79C960_FLUSH_WATCHDOG 5000 /* watchdog timeout - in ms - for TX flush routine */
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/* /ether/am79c960.c */
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extern int am79c960_device_register(int device_no);
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extern void am79c960_device_init_module(void );
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#endif /* __AM79C960_H_LOADED */
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