arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/fake_syscall.cc: arch/alpha/faults.cc: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/circlebuf.cc: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/cprintf.cc: base/cprintf.hh: base/fast_alloc.cc: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/exec_aout.h: base/loader/exec_ecoff.h: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/misc.cc: base/misc.hh: base/pollevent.cc: base/pollevent.hh: base/random.cc: base/random.hh: base/range.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/statistics.cc: base/statistics.hh: base/str.cc: base/trace.cc: base/trace.hh: cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: cpu/pc_event.cc: cpu/pc_event.hh: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.cc: cpu/static_inst.hh: dev/alpha_console.cc: dev/alpha_console.hh: dev/console.cc: dev/console.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/simple_disk.cc: dev/simple_disk.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: sim/debug.cc: sim/eventq.cc: sim/eventq.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/prog.cc: sim/prog.hh: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_object.cc: sim/sim_object.hh: sim/sim_time.cc: sim/system.cc: sim/system.hh: sim/universe.cc: test/circletest.cc: test/cprintftest.cc: test/initest.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/tap/tap.cc: Make include paths explicit. --HG-- extra : convert_revision : 941cbdc591fd4d3d1d9f095cd58fc23dd2d73840
124 lines
4 KiB
C++
124 lines
4 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string>
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#include "targetarch/pmap.h"
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#include "cpu/exec_context.hh"
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#include "mem/functional_mem/physical_memory.hh"
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#include "base/trace.hh"
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#include "targetarch/vtophys.hh"
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using namespace std;
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inline Addr
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level3_index(Addr vaddr)
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{ return (vaddr >> ALPHA_PGSHIFT) & PTEMASK; }
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inline Addr
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level2_index(Addr vaddr)
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{ return (vaddr >> (ALPHA_PGSHIFT + NPTEPG_SHIFT)) & PTEMASK; }
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inline Addr
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level1_index(Addr vaddr)
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{ return (vaddr >> (ALPHA_PGSHIFT + 2 * NPTEPG_SHIFT)) & PTEMASK; }
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Addr
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kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, Addr vaddr)
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{
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uint64_t level1_map = ptbr;
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Addr level1_pte = level1_map + (level1_index(vaddr) << PTESHIFT);
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uint64_t level1 = pmem->phys_read_qword(level1_pte);
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if (!entry_valid(level1)) {
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DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
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return 0;
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}
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uint64_t level2_map = PMAP_PTE_PA(level1);
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Addr level2_pte = level2_map + (level2_index(vaddr) << PTESHIFT);
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uint64_t level2 = pmem->phys_read_qword(level2_pte);
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if (!entry_valid(level2)) {
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DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
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return 0;
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}
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uint64_t level3_map = PMAP_PTE_PA(level2);
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Addr level3_pte = level3_map + (level3_index(vaddr) << PTESHIFT);
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return level3_pte;
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}
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Addr
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vtophys(PhysicalMemory *xc, Addr vaddr)
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{
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Addr paddr = 0;
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if (vaddr < ALPHA_K0SEG_BASE)
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DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
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else if (vaddr < ALPHA_K1SEG_BASE)
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paddr = ALPHA_K0SEG_TO_PHYS(vaddr);
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else
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panic("vtophys: ptbr is not set on virtual lookup");
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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return paddr;
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}
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Addr
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vtophys(ExecContext *xc, Addr vaddr)
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{
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Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
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Addr paddr = 0;
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if (vaddr < ALPHA_K0SEG_BASE) {
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DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
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} else if (vaddr < ALPHA_K1SEG_BASE) {
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paddr = ALPHA_K0SEG_TO_PHYS(vaddr);
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} else {
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if (!ptbr)
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panic("vtophys: ptbr is not set on virtual lookup");
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Addr pte = kernel_pte_lookup(xc->physmem, ptbr, vaddr);
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uint64_t entry = xc->physmem->phys_read_qword(pte);
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if (pte && entry_valid(entry))
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paddr = PMAP_PTE_PA(entry) | (vaddr & PGOFSET);
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}
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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return paddr;
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}
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uint8_t *
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vtomem(ExecContext *xc, Addr vaddr, size_t len)
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{
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Addr paddr = vtophys(xc, vaddr);
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return xc->physmem->dma_addr(paddr, len);
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}
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