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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
Steve Reinhardt 93c4527128 stats: update a few stats from long O3 runs 
Very small changes to iew.predictedNotTakenIncorrect
and iew.branchMispredicts.  Looks like similar updates
were committed on April 3 (changeset 235ff1c046df), but
only for the quick tests.
2015-04-20 15:09:43 -07:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.817778 # Number of seconds simulated
sim_ticks 2817777605000 # Number of ticks simulated
final_tick 2817777605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 307401 # Simulator instruction rate (inst/s)
host_op_rate 373266 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6861547245 # Simulator tick rate (ticks/s)
host_mem_usage 555284 # Number of bytes of host memory used
host_seconds 410.66 # Real time elapsed on the host
sim_insts 126237777 # Number of instructions simulated
sim_ops 153286368 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 655396 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4517280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 125824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1063044 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 5888 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 519744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 4071296 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 10959816 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 655396 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 125824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 519744 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1300964 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8260864 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
system.physmem.bytes_written::total 8278388 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 18694 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 71101 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 1966 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 16611 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 92 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 8121 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 63614 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 180220 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 129076 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
system.physmem.num_writes::total 133457 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 232593 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1603136 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 44654 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 377263 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 2090 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 184452 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 1444861 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3889525 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 232593 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 44654 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 184452 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 461699 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2931695 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2937914 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2931695 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 232593 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1609352 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 44654 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 377266 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 2090 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 184452 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1444861 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6827439 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 90406 # Number of read requests accepted
system.physmem.writeReqs 90720 # Number of write requests accepted
system.physmem.readBursts 90406 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 90720 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 5783616 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 2368 # Total number of bytes read from write queue
system.physmem.bytesWritten 4983552 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 5785924 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 5805960 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 37 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 12831 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 2411 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 5941 # Per bank write bursts
system.physmem.perBankRdBursts::1 5711 # Per bank write bursts
system.physmem.perBankRdBursts::2 5475 # Per bank write bursts
system.physmem.perBankRdBursts::3 5399 # Per bank write bursts
system.physmem.perBankRdBursts::4 5366 # Per bank write bursts
system.physmem.perBankRdBursts::5 5838 # Per bank write bursts
system.physmem.perBankRdBursts::6 6281 # Per bank write bursts
system.physmem.perBankRdBursts::7 6483 # Per bank write bursts
system.physmem.perBankRdBursts::8 6268 # Per bank write bursts
system.physmem.perBankRdBursts::9 6346 # Per bank write bursts
system.physmem.perBankRdBursts::10 5330 # Per bank write bursts
system.physmem.perBankRdBursts::11 5015 # Per bank write bursts
system.physmem.perBankRdBursts::12 5399 # Per bank write bursts
system.physmem.perBankRdBursts::13 5276 # Per bank write bursts
system.physmem.perBankRdBursts::14 4950 # Per bank write bursts
system.physmem.perBankRdBursts::15 5291 # Per bank write bursts
system.physmem.perBankWrBursts::0 4893 # Per bank write bursts
system.physmem.perBankWrBursts::1 4429 # Per bank write bursts
system.physmem.perBankWrBursts::2 4791 # Per bank write bursts
system.physmem.perBankWrBursts::3 4794 # Per bank write bursts
system.physmem.perBankWrBursts::4 4700 # Per bank write bursts
system.physmem.perBankWrBursts::5 5367 # Per bank write bursts
system.physmem.perBankWrBursts::6 5289 # Per bank write bursts
system.physmem.perBankWrBursts::7 5346 # Per bank write bursts
system.physmem.perBankWrBursts::8 5326 # Per bank write bursts
system.physmem.perBankWrBursts::9 5240 # Per bank write bursts
system.physmem.perBankWrBursts::10 4672 # Per bank write bursts
system.physmem.perBankWrBursts::11 4285 # Per bank write bursts
system.physmem.perBankWrBursts::12 5029 # Per bank write bursts
system.physmem.perBankWrBursts::13 5084 # Per bank write bursts
system.physmem.perBankWrBursts::14 4218 # Per bank write bursts
system.physmem.perBankWrBursts::15 4405 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 38 # Number of times write queue was full causing retry
system.physmem.totGap 2816211460500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 1 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 90405 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 90718 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 59525 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 27440 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2853 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 545 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 821 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 982 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 2192 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 2863 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 2992 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3077 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 3147 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 3425 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 3919 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 3373 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 3722 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 4447 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 3652 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 3489 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4724 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 3857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 3769 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 3569 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 777 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 667 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 820 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1468 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1438 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1167 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1245 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1290 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1056 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1082 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 925 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 725 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 728 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 575 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 222 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 98 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 105 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 33321 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 323.130758 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 184.789706 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 346.993140 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 12624 37.89% 37.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 7779 23.35% 61.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 3018 9.06% 70.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1714 5.14% 75.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1413 4.24% 79.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 752 2.26% 81.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 537 1.61% 83.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 554 1.66% 85.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 4930 14.80% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 33321 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 2995 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 30.170618 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 514.809638 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 2993 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 2995 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 2995 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 25.999332 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.796866 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 47.448084 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-15 17 0.57% 0.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31 2784 92.95% 93.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47 41 1.37% 94.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63 11 0.37% 95.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79 6 0.20% 95.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95 14 0.47% 95.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111 11 0.37% 96.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127 12 0.40% 96.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143 7 0.23% 96.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159 11 0.37% 97.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175 7 0.23% 97.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191 15 0.50% 98.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207 14 0.47% 98.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223 4 0.13% 98.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239 1 0.03% 98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255 2 0.07% 98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271 4 0.13% 98.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287 3 0.10% 98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303 3 0.10% 99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319 6 0.20% 99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335 1 0.03% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351 6 0.20% 99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367 5 0.17% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415 1 0.03% 99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495 2 0.07% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527 2 0.07% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543 3 0.10% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559 1 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 2995 # Writes before turning the bus around for reads
system.physmem.totQLat 1193098984 # Total ticks spent queuing
system.physmem.totMemAccLat 2887517734 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 451845000 # Total ticks spent in databus transfers
system.physmem.avgQLat 13202.53 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 31952.53 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.05 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.05 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 4.64 # Average write queue length when enqueuing
system.physmem.readRowHits 74590 # Number of row buffer hits during reads
system.physmem.writeRowHits 60325 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.54 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 77.45 # Row buffer hit rate for writes
system.physmem.avgGap 15548355.62 # Average gap between requests
system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 130667040 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 71094375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 362653200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 256666320 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 178852415040 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 68967490005 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1611945575250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1860586561230 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.497599 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2632498894488 # Time in different power states
system.physmem_0.memoryStateTime::REF 91437840000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 14475823012 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 121239720 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 65934000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 342209400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 247918320 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 178852415040 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 68215091715 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1611413256750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1859258064945 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.496864 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2633620948492 # Time in different power states
system.physmem_1.memoryStateTime::REF 91437840000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 13360607258 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 5755 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 5755 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 5755 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 5755 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 5755 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 166069431868 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.475663 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 87076283368 52.43% 52.43% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 78993148500 47.57% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 166069431868 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 3189 67.65% 67.65% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1525 32.35% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 4714 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5755 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5755 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4714 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4714 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 10469 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 14452204 # DTB read hits
system.cpu0.dtb.read_misses 4833 # DTB read misses
system.cpu0.dtb.write_hits 11089888 # DTB write hits
system.cpu0.dtb.write_misses 922 # DTB write misses
system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3319 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 937 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 14457037 # DTB read accesses
system.cpu0.dtb.write_accesses 11090810 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 25542092 # DTB hits
system.cpu0.dtb.misses 5755 # DTB misses
system.cpu0.dtb.accesses 25547847 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 2817 # Table walker walks requested
system.cpu0.itb.walker.walksShort 2817 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples 2817 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 2817 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 2817 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 166069431868 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.475664 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 87076165368 52.43% 52.43% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 78993266500 47.57% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 166069431868 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 1542 75.55% 75.55% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 499 24.45% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2041 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2817 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2817 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2041 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2041 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 4858 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 67891248 # ITB inst hits
system.cpu0.itb.inst_misses 2817 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 189 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2012 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 67894065 # ITB inst accesses
system.cpu0.itb.hits 67891248 # DTB hits
system.cpu0.itb.misses 2817 # DTB misses
system.cpu0.itb.accesses 67894065 # DTB accesses
system.cpu0.numCycles 82517225 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 66111161 # Number of instructions committed
system.cpu0.committedOps 80627134 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 70885778 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5615 # Number of float alu accesses
system.cpu0.num_func_calls 7285085 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 8754092 # number of instructions that are conditional controls
system.cpu0.num_int_insts 70885778 # number of integer instructions
system.cpu0.num_fp_insts 5615 # number of float instructions
system.cpu0.num_int_register_reads 131498293 # number of times the integer registers were read
system.cpu0.num_int_register_writes 49310474 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 4327 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1292 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 245812611 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 29370316 # number of times the CC registers were written
system.cpu0.num_mem_refs 26208491 # number of memory refs
system.cpu0.num_load_insts 14628012 # Number of load instructions
system.cpu0.num_store_insts 11580479 # Number of store instructions
system.cpu0.num_idle_cycles 77919171.769514 # Number of idle cycles
system.cpu0.num_busy_cycles 4598053.230486 # Number of busy cycles
system.cpu0.not_idle_fraction 0.055722 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.944278 # Percentage of idle cycles
system.cpu0.Branches 16437108 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2194 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 55772206 67.98% 67.98% # Class of executed instruction
system.cpu0.op_class::IntMult 58001 0.07% 68.05% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 4497 0.01% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::MemRead 14628012 17.83% 85.89% # Class of executed instruction
system.cpu0.op_class::MemWrite 11580479 14.11% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 82045389 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 3057 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 831864 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 47054976 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 832376 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 56.530914 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.861119 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.669659 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.466239 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948947 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032558 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018489 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 198551178 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 198551178 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 13770345 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 4433242 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 8498402 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 26701989 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 10695058 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 3174725 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 5187481 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 19057264 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 188196 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 61394 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 132351 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 381941 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234602 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80377 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 136196 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 451175 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236074 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82808 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 140857 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 459739 # number of StoreCondReq hits
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system.cpu0.dcache.demand_hits::cpu1.data 7607967 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 13685883 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 45759253 # number of demand (read+write) hits
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system.cpu0.dcache.overall_hits::cpu1.data 7669361 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 13818234 # number of overall hits
system.cpu0.dcache.overall_hits::total 46141194 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::cpu1.data 59498 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 318451 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 565886 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 147418 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 35026 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 1470502 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1652946 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54526 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 20446 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 66281 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 141253 # number of SoftPFReq misses
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system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3227 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9714 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 17482 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 16 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 335355 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 94524 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1788953 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2218832 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 389881 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 114970 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1855234 # number of overall misses
system.cpu0.dcache.overall_misses::total 2360085 # number of overall misses
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system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4873257385 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5787954377 # number of ReadReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 71024926938 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 72475611266 # number of WriteReq miss cycles
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system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 129200998 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 173051498 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 333505 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 333505 # number of StoreCondReq miss cycles
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system.cpu0.dcache.demand_miss_latency::cpu2.data 75898184323 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 78263565643 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 2365381320 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 75898184323 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 78263565643 # number of overall miss cycles
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system.cpu0.dcache.ReadReq_accesses::cpu1.data 4492740 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 8816853 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 27267875 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::cpu1.data 3209751 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 6657983 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 20710210 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 81840 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 198632 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 523194 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239143 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83604 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 145910 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 468657 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236077 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 82808 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 140873 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 459758 # number of StoreCondReq accesses(hits+misses)
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system.cpu0.dcache.demand_accesses::cpu1.data 7702491 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 15474836 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 47978085 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 25043480 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 7784331 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 15673468 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 48501279 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013464 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013243 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.036118 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.020753 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013596 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.010912 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220863 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.079813 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224644 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.249829 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.333687 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269982 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018989 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.038599 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.066575 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037302 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000013 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000114 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000041 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013522 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012272 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115604 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.046247 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015568 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014769 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118368 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.048660 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15373.575448 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15303.005439 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10228.127886 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41417.356478 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48299.782617 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43846.327264 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13588.627208 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13300.493926 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9898.838691 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 20844.062500 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17552.894737 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25024.134823 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 42426.035968 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 35272.416137 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20573.900322 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 40910.302594 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33161.333445 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 378962 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 29004 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 19067 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 710 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.875282 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 40.850704 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 690587 # number of writebacks
system.cpu0.dcache.writebacks::total 690587 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 87 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 157237 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 157324 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1353907 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1353907 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1937 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6801 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8738 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 87 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 1511144 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1511231 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 87 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 1511144 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1511231 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 59411 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 161214 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 220625 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 35026 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 116595 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 151621 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 20077 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 44216 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 64293 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1290 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 2913 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4203 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 16 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 94437 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 277809 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 372246 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 114514 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 322025 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 436539 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 823130250 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2155055358 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2978185608 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1391922672 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5640631884 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7032554556 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 264066008 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 576983002 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 841049010 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19999250 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 37322251 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57321501 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 309495 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 309495 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2215052922 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7795687242 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 10010740164 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2479118930 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8372670244 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10851789174 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1043159500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1692820000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2735979500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 803109000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1311241000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2114350000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1846268500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3004061000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4850329500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013224 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018285 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008091 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010912 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017512 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007321 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.245320 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.222603 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.122886 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.015430 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019964 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.008968 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000114 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012261 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017952 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.007759 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014711 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020546 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.009001 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13854.845904 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13367.668800 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13498.858280 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.698281 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48377.991200 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46382.457285 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13152.662649 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13049.190384 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13081.502030 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15503.294574 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12812.307243 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13638.234832 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 19343.437500 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19343.437500 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23455.350361 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28061.319979 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26892.807885 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21649.046667 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26000.062865 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24858.693436 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1799096 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.534039 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 100909280 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1799607 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 56.072954 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 10982089250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.173904 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.006307 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 13.353828 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.931980 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.041028 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.026082 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999090 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 104560332 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 104560332 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 67029897 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 21781554 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 12097829 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 100909280 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 67029897 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 21781554 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 12097829 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 100909280 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 67029897 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 21781554 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 12097829 # number of overall hits
system.cpu0.icache.overall_hits::total 100909280 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 863392 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 250227 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 737787 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1851406 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 863392 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 250227 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 737787 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1851406 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 863392 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 250227 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 737787 # number of overall misses
system.cpu0.icache.overall_misses::total 1851406 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3390224750 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10026619709 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 13416844459 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 3390224750 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 10026619709 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 13416844459 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 3390224750 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 10026619709 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 13416844459 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 67893289 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 22031781 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 12835616 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 102760686 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 67893289 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 22031781 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 12835616 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 102760686 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 67893289 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 22031781 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 12835616 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 102760686 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012717 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011358 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057480 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.018017 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012717 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011358 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057480 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.018017 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012717 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011358 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057480 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.018017 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13548.596874 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13590.127922 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 7246.840757 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13548.596874 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13590.127922 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 7246.840757 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13548.596874 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13590.127922 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 7246.840757 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 7212 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 416 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.336538 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 51759 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 51759 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 51759 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 51759 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 51759 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 51759 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 250227 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 686028 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 936255 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 250227 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 686028 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 936255 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 250227 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 686028 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 936255 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 3014176750 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8498569729 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11512746479 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 3014176750 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8498569729 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 11512746479 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 3014176750 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8498569729 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 11512746479 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009111 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.009111 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.009111 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12296.592786 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12296.592786 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12296.592786 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 1874 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 1874 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 637 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1237 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 1874 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 1874 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 1874 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 1601 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12056.839475 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10248.777265 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 6448.828751 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 390 24.36% 24.36% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 856 53.47% 77.83% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 354 22.11% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 1601 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 1000015500 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1000015500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1000015500 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 972 60.71% 60.71% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 629 39.29% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 1601 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1874 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1874 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1601 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1601 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 3475 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 4664064 # DTB read hits
system.cpu1.dtb.read_misses 1628 # DTB read misses
system.cpu1.dtb.write_hits 3297220 # DTB write hits
system.cpu1.dtb.write_misses 246 # DTB write misses
system.cpu1.dtb.flush_tlb 168 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 112 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1307 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 60 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 4665692 # DTB read accesses
system.cpu1.dtb.write_accesses 3297466 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 7961284 # DTB hits
system.cpu1.dtb.misses 1874 # DTB misses
system.cpu1.dtb.accesses 7963158 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 876 # Table walker walks requested
system.cpu1.itb.walker.walksShort 876 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 230 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 646 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 876 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 876 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 876 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 692 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12877.167630 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11119.022104 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 6272.001420 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::2048-4095 140 20.23% 20.23% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::10240-12287 230 33.24% 53.47% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-14335 143 20.66% 74.13% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-22527 156 22.54% 96.68% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::22528-24575 23 3.32% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 692 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 462 66.76% 66.76% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 230 33.24% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 692 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 876 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 876 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 692 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 692 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 1568 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 22031781 # ITB inst hits
system.cpu1.itb.inst_misses 876 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 168 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 112 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 752 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 22032657 # ITB inst accesses
system.cpu1.itb.hits 22031781 # DTB hits
system.cpu1.itb.misses 876 # DTB misses
system.cpu1.itb.accesses 22032657 # DTB accesses
system.cpu1.numCycles 158012603 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 21317281 # Number of instructions committed
system.cpu1.committedOps 25549926 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 22701009 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1608 # Number of float alu accesses
system.cpu1.num_func_calls 2410952 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 2737582 # number of instructions that are conditional controls
system.cpu1.num_int_insts 22701009 # number of integer instructions
system.cpu1.num_fp_insts 1608 # number of float instructions
system.cpu1.num_int_register_reads 41843043 # number of times the integer registers were read
system.cpu1.num_int_register_writes 15920660 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1288 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 320 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 92840963 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 9448697 # number of times the CC registers were written
system.cpu1.num_mem_refs 8172131 # number of memory refs
system.cpu1.num_load_insts 4710232 # Number of load instructions
system.cpu1.num_store_insts 3461899 # Number of store instructions
system.cpu1.num_idle_cycles 151539718.287508 # Number of idle cycles
system.cpu1.num_busy_cycles 6472884.712492 # Number of busy cycles
system.cpu1.not_idle_fraction 0.040964 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.959036 # Percentage of idle cycles
system.cpu1.Branches 5298424 # Number of branches fetched
system.cpu1.op_class::No_OpClass 41 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 18071289 68.81% 68.81% # Class of executed instruction
system.cpu1.op_class::IntMult 19339 0.07% 68.88% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 1186 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction
system.cpu1.op_class::MemRead 4710232 17.93% 86.82% # Class of executed instruction
system.cpu1.op_class::MemWrite 3461899 13.18% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 26263986 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 17390044 # Number of BP lookups
system.cpu2.branchPred.condPredicted 9451928 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 400737 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 10830418 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 8125283 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 75.022802 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 4068079 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 21097 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.dtb.walker.walks 43271 # Table walker walks requested
system.cpu2.dtb.walker.walksShort 43271 # Table walker walks initiated with short descriptors
system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13795 # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 11030 # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walksSquashedBefore 18446 # Table walks squashed before starting
system.cpu2.dtb.walker.walkWaitTime::samples 24825 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::mean 526.888218 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::stdev 3382.784717 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0-16383 24602 99.10% 99.10% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::16384-32767 180 0.73% 99.83% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::32768-49151 23 0.09% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::49152-65535 14 0.06% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::65536-81919 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::98304-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total 24825 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples 9018 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 12445.276336 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 10074.043051 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 7598.717395 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-8191 2712 30.07% 30.07% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::8192-16383 3866 42.87% 72.94% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2205 24.45% 97.39% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::24576-32767 103 1.14% 98.54% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::32768-40959 58 0.64% 99.18% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::40960-49151 71 0.79% 99.97% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total 9018 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples 60407494468 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::mean 0.614556 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::stdev 0.505382 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0-1 60349981968 99.90% 99.90% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::2-3 42488500 0.07% 99.98% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::4-5 7802000 0.01% 99.99% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::6-7 2924500 0.00% 99.99% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::8-9 1368500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::10-11 844500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::12-13 331000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::14-15 1040000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::16-17 124500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::18-19 121000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::20-21 186000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::22-23 81500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::24-25 109000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::26-27 11000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::28-29 5500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::30-31 75000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 60407494468 # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K 2796 73.35% 73.35% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::1M 1016 26.65% 100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total 3812 # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43271 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43271 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3812 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3812 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total 47083 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
system.cpu2.dtb.read_hits 9630626 # DTB read hits
system.cpu2.dtb.read_misses 37535 # DTB read misses
system.cpu2.dtb.write_hits 7130235 # DTB write hits
system.cpu2.dtb.write_misses 5736 # DTB write misses
system.cpu2.dtb.flush_tlb 179 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 360 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 2330 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 520 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 952 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults 414 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 9668161 # DTB read accesses
system.cpu2.dtb.write_accesses 7135971 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
system.cpu2.dtb.hits 16760861 # DTB hits
system.cpu2.dtb.misses 43271 # DTB misses
system.cpu2.dtb.accesses 16804132 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.itb.walker.walks 6235 # Table walker walks requested
system.cpu2.itb.walker.walksShort 6235 # Table walker walks initiated with short descriptors
system.cpu2.itb.walker.walksShortTerminationLevel::Level1 2044 # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4088 # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walksSquashedBefore 103 # Table walks squashed before starting
system.cpu2.itb.walker.walkWaitTime::samples 6132 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::mean 1114.562948 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::stdev 4869.153513 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0-8191 5831 95.09% 95.09% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::8192-16383 152 2.48% 97.57% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::16384-24575 99 1.61% 99.18% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::24576-32767 29 0.47% 99.66% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::32768-40959 9 0.15% 99.80% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::40960-49151 4 0.07% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::49152-57343 3 0.05% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::57344-65535 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::65536-73727 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::106496-114687 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total 6132 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples 1857 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 12539.311255 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 10038.361952 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 8040.211817 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-4095 547 29.46% 29.46% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::4096-8191 43 2.32% 31.77% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::8192-12287 410 22.08% 53.85% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::12288-16383 373 20.09% 73.94% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::16384-20479 9 0.48% 74.42% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::20480-24575 413 22.24% 96.66% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::24576-28671 14 0.75% 97.42% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::28672-32767 13 0.70% 98.12% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-36863 11 0.59% 98.71% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::36864-40959 8 0.43% 99.14% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::40960-45055 10 0.54% 99.68% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::45056-49151 1 0.05% 99.73% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::49152-53247 1 0.05% 99.78% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::53248-57343 2 0.11% 99.89% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::57344-61439 1 0.05% 99.95% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::61440-65535 1 0.05% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total 1857 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples 13162833212 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::mean 0.828087 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::stdev 0.377922 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2265327000 17.21% 17.21% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::1 10895443212 82.77% 99.98% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::2 1802500 0.01% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::3 162000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::4 51500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::5 47000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 13162833212 # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K 1358 77.42% 77.42% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::1M 396 22.58% 100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total 1754 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 6235 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total 6235 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1754 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1754 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total 7989 # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits 12837123 # ITB inst hits
system.cpu2.itb.inst_misses 6235 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 179 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 360 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 1683 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults 1125 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.inst_accesses 12843358 # ITB inst accesses
system.cpu2.itb.hits 12837123 # DTB hits
system.cpu2.itb.misses 6235 # DTB misses
system.cpu2.itb.accesses 12843358 # DTB accesses
system.cpu2.numCycles 69616646 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 26594039 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 69071466 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 17390044 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 12193362 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 39655163 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 2070826 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 93322 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 918 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 302 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 323029 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 106475 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 727 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 12835626 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 269064 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 2716 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 67809362 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.223662 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.348600 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 49260090 72.64% 72.64% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 2390617 3.53% 76.17% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 1561768 2.30% 78.47% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 4865604 7.18% 85.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 1097205 1.62% 87.27% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 701816 1.03% 88.30% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 3870082 5.71% 94.01% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 751059 1.11% 95.12% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 3311121 4.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 67809362 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.249797 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.992169 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 18546973 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 36871218 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 10413141 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 1051163 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 926599 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 1313756 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 110434 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 59271705 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 356279 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 926599 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 19159512 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 3828211 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 27033628 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 10840093 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 6021054 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 56800254 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 1622 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 892733 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 160451 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 4475802 # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands 58727822 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 260839498 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 63695069 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 4195 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 48596346 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 10131460 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 953771 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 889969 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 6004915 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 10275852 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 7909386 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 1396867 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 1932490 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 54546075 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 673336 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 51866821 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 68048 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 7293157 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 18430167 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 68913 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 67809362 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 0.764892 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.469149 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 47470041 70.01% 70.01% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 6738750 9.94% 79.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 5086869 7.50% 87.44% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 4143776 6.11% 93.56% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 1653610 2.44% 95.99% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 1071590 1.58% 97.57% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 1124885 1.66% 99.23% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 357423 0.53% 99.76% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 162418 0.24% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 67809362 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 76711 9.73% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 2 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 365050 46.29% 56.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 346827 43.98% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 102 0.00% 0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 34390478 66.31% 66.31% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 39542 0.08% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 1 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 2888 0.01% 66.39% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.39% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 66.39% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.39% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 9917724 19.12% 85.51% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 7516080 14.49% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 51866821 # Type of FU issued
system.cpu2.iq.rate 0.745035 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 788590 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.015204 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 172390251 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 62545050 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 50322136 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 9391 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 4963 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 4144 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 52650258 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 5051 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 268895 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 1610409 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 1859 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 38198 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 800698 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 130635 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 68542 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 926599 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 3277236 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 403345 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 55328961 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 92252 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 10275852 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 7909386 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 360332 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 33301 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 361214 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 38198 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 183568 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 164696 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 348264 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 51429187 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 9738477 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 394455 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 109550 # number of nop insts executed
system.cpu2.iew.exec_refs 17180160 # number of memory reference insts executed
system.cpu2.iew.exec_branches 9476518 # Number of branches executed
system.cpu2.iew.exec_stores 7441683 # Number of stores executed
system.cpu2.iew.exec_rate 0.738748 # Inst execution rate
system.cpu2.iew.wb_sent 51031347 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 50326280 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 26469079 # num instructions producing a value
system.cpu2.iew.wb_consumers 46041332 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 0.722906 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.574898 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 8143906 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 604423 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 291897 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 66086949 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 0.713825 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.622364 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 48131767 72.83% 72.83% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 7989880 12.09% 84.92% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 3968576 6.01% 90.93% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 1690353 2.56% 93.48% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 906489 1.37% 94.86% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 608385 0.92% 95.78% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 1262051 1.91% 97.69% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 299318 0.45% 98.14% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 1230130 1.86% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 66086949 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 38874571 # Number of instructions committed
system.cpu2.commit.committedOps 47174544 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 15774131 # Number of memory references committed
system.cpu2.commit.loads 8665443 # Number of loads committed
system.cpu2.commit.membars 227144 # Number of memory barriers committed
system.cpu2.commit.branches 8900555 # Number of branches committed
system.cpu2.commit.fp_insts 4112 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 41283041 # Number of committed integer instructions.
system.cpu2.commit.function_calls 1636102 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 31359241 66.47% 66.47% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 38284 0.08% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 2888 0.01% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 8665443 18.37% 84.93% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 7108688 15.07% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 47174544 # Class of committed instruction
system.cpu2.commit.bw_lim_events 1230130 # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads 112818862 # The number of ROB reads
system.cpu2.rob.rob_writes 112362949 # The number of ROB writes
system.cpu2.timesIdled 279332 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 1807284 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 5249914577 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 38809335 # Number of Instructions Simulated
system.cpu2.committedOps 47109308 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.793812 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.793812 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.557472 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.557472 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 56301107 # number of integer regfile reads
system.cpu2.int_regfile_writes 31916155 # number of integer regfile writes
system.cpu2.fp_regfile_reads 15723 # number of floating regfile reads
system.cpu2.fp_regfile_writes 13758 # number of floating regfile writes
system.cpu2.cc_regfile_reads 181999487 # number of cc regfile reads
system.cpu2.cc_regfile_writes 19225356 # number of cc regfile writes
system.cpu2.misc_regfile_reads 123907195 # number of misc regfile reads
system.cpu2.misc_regfile_writes 485009 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 30180 # Transaction distribution
system.iobus.trans_dist::ReadResp 30180 # Transaction distribution
system.iobus.trans_dist::WriteReq 59003 # Transaction distribution
system.iobus.trans_dist::WriteResp 22779 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54126 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105414 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178366 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67843 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159071 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480319 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 18225000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 2714000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15729000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 124959118 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 39808000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 23061006 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36442 # number of replacements
system.iocache.tags.tagsinuse 0.992064 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 244950709509 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 0.992064 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062004 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062004 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 252 # number of overall misses
system.iocache.overall_misses::total 252 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 14858930 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 14858930 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 4185043182 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 4185043182 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide 14858930 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 14858930 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 14858930 # number of overall miss cycles
system.iocache.overall_miss_latency::total 14858930 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 58964.007937 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 58964.007937 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 115532.331659 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 115532.331659 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 58964.007937 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 58964.007937 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 58964.007937 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 58964.007937 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 14316 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 2165 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 6.612471 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 125 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 22752 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 22752 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 125 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 125 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 125 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 125 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 8240930 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 8240930 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 3001927194 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 3001927194 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 8240930 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8240930 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 8240930 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8240930 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.496032 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.628092 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.628092 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.496032 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.496032 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 65927.440000 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 65927.440000 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131941.244462 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131941.244462 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 65927.440000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 65927.440000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 65927.440000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 65927.440000 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 100862 # number of replacements
system.l2c.tags.tagsinuse 65121.580421 # Cycle average of tags in use
system.l2c.tags.total_refs 2889469 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 166056 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 17.400570 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 49829.873035 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939329 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5354.052994 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2949.398573 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969230 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1018.817810 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 810.859726 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 62.513746 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 3585.332677 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 1507.823205 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.760344 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.081696 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.045004 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.015546 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.012373 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000954 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.054708 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.023008 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.993676 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65144 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2979 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 8228 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 53568 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000763 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.994019 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 27412273 # Number of tag accesses
system.l2c.tags.data_accesses 27412273 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 4625 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 2417 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 853709 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 239887 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 1714 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 910 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 248258 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 78311 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 26936 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 6133 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 677801 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 203846 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2344547 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 690587 # number of Writeback hits
system.l2c.Writeback_hits::total 690587 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 33 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data 10 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 81710 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 20207 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 55512 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 157429 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 4625 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 2417 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 853709 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 321597 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 1714 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 910 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 248258 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 98518 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 26936 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 6133 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 677801 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 259358 # number of demand (read+write) hits
system.l2c.demand_hits::total 2501976 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 4625 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 2417 # number of overall hits
system.l2c.overall_hits::cpu0.inst 853709 # number of overall hits
system.l2c.overall_hits::cpu0.data 321597 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 1714 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 910 # number of overall hits
system.l2c.overall_hits::cpu1.inst 248258 # number of overall hits
system.l2c.overall_hits::cpu1.data 98518 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 26936 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 6133 # number of overall hits
system.l2c.overall_hits::cpu2.inst 677801 # number of overall hits
system.l2c.overall_hits::cpu2.data 259358 # number of overall hits
system.l2c.overall_hits::total 2501976 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 9677 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 7117 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 1966 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 2467 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 92 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 8131 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 4488 # number of ReadReq misses
system.l2c.ReadReq_misses::total 33944 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1342 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 299 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 1074 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2715 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 3 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu2.data 6 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 9 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 64356 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 14516 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 59985 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 138857 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 9677 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 71473 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 1966 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 16983 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 92 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 8131 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 64473 # number of demand (read+write) misses
system.l2c.demand_misses::total 172801 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.inst 9677 # number of overall misses
system.l2c.overall_misses::cpu0.data 71473 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 1966 # number of overall misses
system.l2c.overall_misses::cpu1.data 16983 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 92 # number of overall misses
system.l2c.overall_misses::cpu2.inst 8131 # number of overall misses
system.l2c.overall_misses::cpu2.data 64473 # number of overall misses
system.l2c.overall_misses::total 172801 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 82500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 157235750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 203986258 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7890000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 682853750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 390763250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1442811508 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 93497 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 280991 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 374488 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu2.data 63499 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 63499 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1135317971 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 4897657997 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6032975968 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 82500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 157235750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1339304229 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 7890000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 682853750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 5288421247 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 7475787476 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 82500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 157235750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1339304229 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 7890000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 682853750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 5288421247 # number of overall miss cycles
system.l2c.overall_miss_latency::total 7475787476 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4629 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 2418 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 863386 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 247004 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 1715 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 910 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 250224 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 80778 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 27028 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 6133 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 685932 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 208334 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2378491 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 690587 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 690587 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1352 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 303 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 1107 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2762 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 3 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data 16 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 146066 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 34723 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 115497 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 296286 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 4629 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 2418 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 863386 # number of demand (read+write) accesses
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system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69541.309084 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 69076.292636 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 74250 # Transaction distribution
system.membus.trans_dist::ReadResp 74249 # Transaction distribution
system.membus.trans_dist::WriteReq 27555 # Transaction distribution
system.membus.trans_dist::WriteResp 27555 # Transaction distribution
system.membus.trans_dist::Writeback 129076 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4552 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 9 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4561 # Transaction distribution
system.membus.trans_dist::ReadExReq 137020 # Transaction distribution
system.membus.trans_dist::ReadExResp 137020 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105414 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471581 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 578995 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109017 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 109017 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 688012 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159071 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16928828 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 17091899 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642624 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4642624 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 21734523 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 283 # Total snoops (count)
system.membus.snoop_fanout::samples 341064 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 341064 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 341064 # Request fanout histogram
system.membus.reqLayer0.occupancy 45631500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 463000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 565034415 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 525270598 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 23441994 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 2441800 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2441792 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27555 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27555 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 690587 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 22777 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2762 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 19 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2781 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3617238 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2478347 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29055 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87637 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 6212277 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115207096 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97661699 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48712 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154828 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 213072335 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 51752 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 3427725 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 3.010649 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.102642 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 3391224 98.94% 98.94% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 36501 1.06% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 3427725 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 1275217471 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 177000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 1406471499 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 694961258 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 11749485 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 39124219 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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