25e1b1c1f5
This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
640 lines
73 KiB
Text
640 lines
73 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.230173 # Number of seconds simulated
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sim_ticks 230173358500 # Number of ticks simulated
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final_tick 230173358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1194511 # Simulator instruction rate (inst/s)
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host_op_rate 1259316 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1599980237 # Simulator tick rate (ticks/s)
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host_mem_usage 316228 # Number of bytes of host memory used
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host_seconds 143.86 # Real time elapsed on the host
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sim_insts 171842484 # Number of instructions simulated
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sim_ops 181165371 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory
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system.physmem.bytes_read::total 220992 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.dtb.walker.walks 0 # Table walker walks requested
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system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.itb.walker.walks 0 # Table walker walks requested
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system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 400 # Number of system calls
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system.cpu.numCycles 460346717 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 171842484 # Number of instructions committed
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system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
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system.cpu.num_func_calls 3545028 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls
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system.cpu.num_int_insts 143085668 # number of integer instructions
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system.cpu.num_fp_insts 1752310 # number of float instructions
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system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read
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system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
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system.cpu.num_cc_register_reads 626384530 # number of times the CC registers were read
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system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
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system.cpu.num_mem_refs 40540779 # number of memory refs
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system.cpu.num_load_insts 27896144 # Number of load instructions
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system.cpu.num_store_insts 12644635 # Number of store instructions
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system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
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system.cpu.num_busy_cycles 460346716.998000 # Number of busy cycles
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system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
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system.cpu.Branches 40300312 # Number of branches fetched
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system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
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system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction
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system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
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system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
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system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 181650743 # Class of executed instruction
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system.cpu.dcache.tags.replacements 40 # number of replacements
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system.cpu.dcache.tags.tagsinuse 1363.619267 # Cycle average of tags in use
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system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks.
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system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
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system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks.
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system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619267 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id
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system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses
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system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses
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system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
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system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
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system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
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system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits
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system.cpu.dcache.overall_hits::total 40117812 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
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system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
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system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1789 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 16 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34781000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 34781000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59094500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 59094500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93875500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 93875500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93929500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 93929500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50553.779070 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50553.779070 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53722.272727 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53722.272727 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52503.076063 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52503.076063 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52503.912800 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52503.912800 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 1506 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1147.992590 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992590 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 189857002 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 189857002 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 189857002 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 3051 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 189860053 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 189860053 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 189860053 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109320000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 109320000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109320000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 109320000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109320000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 109320000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35830.875123 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35830.875123 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 1675.663321 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036732 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588811 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses
|
|
system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 1322 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 57 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 57 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1387 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1729 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 1729 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 3453 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57360500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 57360500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 90862500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 90862500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33203000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 33203000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 90862500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 90563500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 181426000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 90862500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 90563500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 181426000 # number of overall miss cycles
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3051 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 3051 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 689 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 689 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.566699 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.917271 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.917271 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52552.053210 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52536.392405 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52536.392405 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1729 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 632 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 632 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46440500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46440500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73572500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73572500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 26883000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 26883000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73572500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73323500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 146896000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73572500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73323500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 146896000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.566699 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42527.930403 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42527.930403 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42552.053210 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42552.053210 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42536.392405 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42536.392405 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42552.053210 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42552.053210 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 1466 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7550 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3612 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 11162 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 6386 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 6386 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 6386 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 3209000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 2361 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 2361 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 3453 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 3453 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|