3341 lines
391 KiB
Plaintext
3341 lines
391 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.824356 # Number of seconds simulated
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sim_ticks 2824356167500 # Number of ticks simulated
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final_tick 2824356167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 95847 # Simulator instruction rate (inst/s)
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host_op_rate 116283 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2253286315 # Simulator tick rate (ticks/s)
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host_mem_usage 605880 # Number of bytes of host memory used
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host_seconds 1253.44 # Real time elapsed on the host
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sim_insts 120137953 # Number of instructions simulated
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sim_ops 145753814 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.inst 208 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 336 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu1.inst 208 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 336 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.inst 74 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 119 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu1.inst 74 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 119 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.inst 74 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 119 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 286048 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 1048060 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.l2cache.prefetcher 10518784 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 32848 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 551328 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.l2cache.prefetcher 1337024 # Number of bytes read from this memory
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system.physmem.bytes_read::total 13777996 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 286048 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 32848 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 318896 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7262976 # Number of bytes written to this memory
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system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
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system.physmem.bytes_written::total 9599056 # Number of bytes written to this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 31 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 6715 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 16901 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.l2cache.prefetcher 164356 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 580 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 8638 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.l2cache.prefetcher 20891 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 218142 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 113484 # Number of write requests responded to by this memory
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system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 154144 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 702 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 101279 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 371079 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.l2cache.prefetcher 3724312 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 249 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 11630 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 195205 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.l2cache.prefetcher 473391 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 4878279 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 101279 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 11630 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 112909 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2571551 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::realview.ide 820837 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 3398671 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2571551 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 821177 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 702 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 101279 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 377348 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.l2cache.prefetcher 3724312 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 11630 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 195219 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.l2cache.prefetcher 473391 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 8276949 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 218142 # Number of read requests accepted
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system.physmem.writeReqs 154144 # Number of write requests accepted
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system.physmem.readBursts 218142 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 154144 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 13946624 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 14464 # Total number of bytes read from write queue
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system.physmem.bytesWritten 9613440 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 13777996 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 9599056 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 226 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 13812 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 13742 # Per bank write bursts
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system.physmem.perBankRdBursts::1 13629 # Per bank write bursts
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system.physmem.perBankRdBursts::2 14383 # Per bank write bursts
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system.physmem.perBankRdBursts::3 14277 # Per bank write bursts
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system.physmem.perBankRdBursts::4 15951 # Per bank write bursts
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system.physmem.perBankRdBursts::5 13005 # Per bank write bursts
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system.physmem.perBankRdBursts::6 13913 # Per bank write bursts
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system.physmem.perBankRdBursts::7 13901 # Per bank write bursts
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system.physmem.perBankRdBursts::8 13634 # Per bank write bursts
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system.physmem.perBankRdBursts::9 13374 # Per bank write bursts
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system.physmem.perBankRdBursts::10 12813 # Per bank write bursts
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system.physmem.perBankRdBursts::11 11699 # Per bank write bursts
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system.physmem.perBankRdBursts::12 13387 # Per bank write bursts
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system.physmem.perBankRdBursts::13 14173 # Per bank write bursts
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system.physmem.perBankRdBursts::14 13330 # Per bank write bursts
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system.physmem.perBankRdBursts::15 12705 # Per bank write bursts
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system.physmem.perBankWrBursts::0 9697 # Per bank write bursts
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system.physmem.perBankWrBursts::1 9775 # Per bank write bursts
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system.physmem.perBankWrBursts::2 10292 # Per bank write bursts
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system.physmem.perBankWrBursts::3 9920 # Per bank write bursts
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system.physmem.perBankWrBursts::4 9082 # Per bank write bursts
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system.physmem.perBankWrBursts::5 9049 # Per bank write bursts
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system.physmem.perBankWrBursts::6 9470 # Per bank write bursts
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system.physmem.perBankWrBursts::7 9454 # Per bank write bursts
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system.physmem.perBankWrBursts::8 9424 # Per bank write bursts
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system.physmem.perBankWrBursts::9 9315 # Per bank write bursts
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system.physmem.perBankWrBursts::10 9173 # Per bank write bursts
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system.physmem.perBankWrBursts::11 8636 # Per bank write bursts
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system.physmem.perBankWrBursts::12 9486 # Per bank write bursts
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system.physmem.perBankWrBursts::13 9567 # Per bank write bursts
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system.physmem.perBankWrBursts::14 9156 # Per bank write bursts
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system.physmem.perBankWrBursts::15 8714 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
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system.physmem.totGap 2824354558500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 559 # Read request sizes (log2)
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system.physmem.readPktSize::3 28 # Read request sizes (log2)
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system.physmem.readPktSize::4 3083 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 214472 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 4436 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 149708 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 53602 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 76817 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 20742 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 15242 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 11051 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 9710 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 8839 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 8210 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 7163 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 2472 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1433 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1086 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 621 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 437 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 277 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 206 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 2929 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 3545 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4158 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4869 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5623 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 6990 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 7782 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 8751 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 9680 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 10891 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 10789 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 10809 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 10760 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 11318 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 9435 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 9260 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 9292 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 8709 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 893 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 622 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 394 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 295 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 223 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 198 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 192 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 167 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 165 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 126 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 85 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 62 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 33 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 92866 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 253.699567 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 143.705803 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 308.390709 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 46941 50.55% 50.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 18915 20.37% 70.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 6813 7.34% 78.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 3565 3.84% 82.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 3222 3.47% 85.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 2153 2.32% 87.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 1230 1.32% 89.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 1078 1.16% 90.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 8949 9.64% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 92866 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 7533 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 28.928183 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 527.934330 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-2047 7532 99.99% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 7533 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 7533 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 19.940263 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 18.639504 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 10.756386 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 6124 81.30% 81.30% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 560 7.43% 88.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 110 1.46% 90.19% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 221 2.93% 93.12% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 195 2.59% 95.71% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 21 0.28% 95.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 17 0.23% 96.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 21 0.28% 96.50% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 30 0.40% 96.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 8 0.11% 97.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 3 0.04% 97.04% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 3 0.04% 97.08% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 162 2.15% 99.23% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 7 0.09% 99.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 6 0.08% 99.40% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 5 0.07% 99.47% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 13 0.17% 99.64% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 1 0.01% 99.65% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 1 0.01% 99.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 7 0.09% 99.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 2 0.03% 99.79% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-107 1 0.01% 99.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 1 0.01% 99.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 2 0.03% 99.84% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::116-119 3 0.04% 99.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 1 0.01% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 3 0.04% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 3 0.04% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 7533 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 8921648500 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 13007573500 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 1089580000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 40940.77 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 59690.77 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 3.40 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.07 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 22.17 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 185257 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 90003 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 85.01 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 59.91 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 7586518.32 # Average gap between requests
|
|
system.physmem.pageHitRate 74.77 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 2697281054000 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 94311360000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 32761026000 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem.actEnergy::0 364739760 # Energy for activate commands per rank (pJ)
|
|
system.physmem.actEnergy::1 337327200 # Energy for activate commands per rank (pJ)
|
|
system.physmem.preEnergy::0 199014750 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.preEnergy::1 184057500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.readEnergy::0 879847800 # Energy for read commands per rank (pJ)
|
|
system.physmem.readEnergy::1 819897000 # Energy for read commands per rank (pJ)
|
|
system.physmem.writeEnergy::0 497268720 # Energy for write commands per rank (pJ)
|
|
system.physmem.writeEnergy::1 476092080 # Energy for write commands per rank (pJ)
|
|
system.physmem.refreshEnergy::0 184473020160 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.refreshEnergy::1 184473020160 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.actBackEnergy::0 78882264090 # Energy for active background per rank (pJ)
|
|
system.physmem.actBackEnergy::1 78474830085 # Energy for active background per rank (pJ)
|
|
system.physmem.preBackEnergy::0 1625417087250 # Energy for precharge background per rank (pJ)
|
|
system.physmem.preBackEnergy::1 1625774485500 # Energy for precharge background per rank (pJ)
|
|
system.physmem.totalEnergy::0 1890713242530 # Total energy per rank (pJ)
|
|
system.physmem.totalEnergy::1 1890539709525 # Total energy per rank (pJ)
|
|
system.physmem.averagePower::0 669.432241 # Core power per rank (mW)
|
|
system.physmem.averagePower::1 669.370799 # Core power per rank (mW)
|
|
system.membus.trans_dist::ReadReq 237803 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 237803 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 30981 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 30981 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 113484 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 79622 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 40753 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 13812 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 31225 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 14907 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13750 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 709115 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 830877 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 903587 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 336 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27500 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21057756 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 21248442 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 23567738 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 123113 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 501114 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 501114 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 501114 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 81319989 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 11512493 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 1643090249 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 2114237552 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 38543657 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.l2c.tags.replacements 153338 # number of replacements
|
|
system.l2c.tags.tagsinuse 64407.351795 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 520948 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 218016 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 2.389494 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 14039.109160 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 10.926266 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 1.063683 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 1406.687456 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 2124.369402 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39350.084930 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.463090 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.906491 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 305.066680 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 911.182744 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6250.491894 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.214220 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000167 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.021464 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.032415 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.600435 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000114 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.004655 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.013904 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.095375 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.982778 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1022 44311 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 20347 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1022::2 406 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1022::3 7760 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1022::4 36145 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 4612 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 15362 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1022 0.676132 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.310471 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 6600636 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 6600636 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 292 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 154 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 12492 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 39083 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182457 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 82 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 48 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 4094 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 11500 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44186 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 294388 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 252842 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 252842 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 11706 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 12433 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 197 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 154 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 351 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 3674 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 1157 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 4831 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 292 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 154 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 12492 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 42757 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.l2cache.prefetcher 182457 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 82 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 48 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 4094 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 12657 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.l2cache.prefetcher 44186 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 299219 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 292 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 154 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 12492 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 42757 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.l2cache.prefetcher 182457 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 82 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 48 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 4094 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 12657 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.l2cache.prefetcher 44186 # number of overall hits
|
|
system.l2c.overall_hits::total 299219 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 31 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 3722 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 8649 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164359 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 492 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 1396 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 20906 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 199570 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 8911 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 2815 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 11726 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 768 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 1215 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1983 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 7775 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 7235 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 15010 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 31 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 3722 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 16424 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.l2cache.prefetcher 164359 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 492 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 8631 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.l2cache.prefetcher 20906 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 214580 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 31 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 3722 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 16424 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.l2cache.prefetcher 164359 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 492 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 8631 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.l2cache.prefetcher 20906 # number of overall misses
|
|
system.l2c.overall_misses::total 214580 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2653000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 225500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 348764246 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 769947990 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 875000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 50097250 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 119367500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 22807506228 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 7178208 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 2570892 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 9749100 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1432440 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 791466 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 2223906 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 708658416 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 564088479 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 1272746895 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 2653000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 225500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 348764246 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 1478606406 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 875000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 50097250 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 683455979 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 24080253123 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 2653000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 225500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 348764246 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 1478606406 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 875000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 50097250 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 683455979 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 24080253123 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 323 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 157 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 16214 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 47732 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346816 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 93 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 49 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 4586 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 12896 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65092 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 493958 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 252842 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 252842 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 20617 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 3542 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 24159 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 965 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 1369 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 2334 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 11449 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 8392 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 19841 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 323 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 157 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 16214 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 59181 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346816 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 93 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 49 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 4586 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 21288 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65092 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 513799 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 323 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 157 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 16214 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 59181 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 346816 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 93 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 49 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 4586 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 21288 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65092 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 513799 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019108 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.229555 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.181199 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020408 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.107283 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.108251 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.404022 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.432216 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.794749 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.485368 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.795855 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.887509 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.849614 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.679099 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.862131 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.756514 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.019108 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.229555 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.277522 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.itb.walker 0.020408 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.107283 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.405440 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.417634 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.019108 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.229555 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.277522 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.itb.walker 0.020408 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.107283 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.405440 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.417634 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75166.666667 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 93703.451370 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 89021.619840 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 101823.678862 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 85506.805158 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 114283.240106 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 805.544608 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 913.283126 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 831.408835 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1865.156250 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 651.412346 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 1121.485628 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91145.776977 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77966.617692 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 84793.264157 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75166.666667 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 93703.451370 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 90027.180102 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 101823.678862 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 79186.186884 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 112220.398560 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75166.666667 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 93703.451370 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 90027.180102 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 101823.678862 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 79186.186884 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 112220.398560 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 435 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 26 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs 16.730769 # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 113484 # number of writebacks
|
|
system.l2c.writebacks::total 113484 # number of writebacks
|
|
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 3 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 15 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 3 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 15 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 3 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 15 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 31 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 3721 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 8649 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 491 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 1396 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 199550 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 8911 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 2815 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 11726 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 768 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1215 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1983 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 7775 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 7235 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 15010 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.dtb.walker 31 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 3721 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 16424 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 491 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 8631 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 214560 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.dtb.walker 31 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 3721 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 16424 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 491 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 8631 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 214560 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 187500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 302749246 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 662570490 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 738500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 43998750 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 101980500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 20353955728 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 90147824 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28509296 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 118657120 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7897727 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12233707 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 20131434 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 612435582 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 472780517 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 1085216099 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 187500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 302749246 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 1275006072 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 738500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 43998750 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 574761017 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 21439171827 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 187500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 302749246 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 1275006072 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 738500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 43998750 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 574761017 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 21439171827 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 158715000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3685804000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5055250 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919801500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 5769375750 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713908502 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535177501 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 4249086003 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 158715000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6399712502 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5055250 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3454979001 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 10018461753 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181199 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.108251 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.403982 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.432216 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.794749 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.485368 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795855 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.887509 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.849614 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.679099 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.862131 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.756514 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.277522 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.405440 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.417595 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.277522 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.405440 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.417595 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76606.600763 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73051.934097 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 101999.277013 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10116.465492 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10127.636234 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10119.147194 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10283.498698 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10068.894650 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10152.009077 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78769.849775 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65346.305045 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72299.540240 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77630.666829 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66592.633183 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 99921.568918 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77630.666829 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66592.633183 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 99921.568918 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
|
system.toL2Bus.trans_dist::ReadReq 660507 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 660492 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 30981 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 30981 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 252842 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 91952 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 41104 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 133056 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 40101 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 40101 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1300560 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426210 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 1726770 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40798474 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8541616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 49340090 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 291850 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 1084776 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 1.033629 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.180273 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 1048296 96.64% 96.64% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 36480 3.36% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 1084776 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 1587917075 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 2276216676 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 846189675 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 31016 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 31016 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateReq 21 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 180912 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2484058 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 326647327 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 36834343 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.branchPred.lookups 24027935 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 15717476 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 977431 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 14651046 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 10773468 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 73.533780 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 3878036 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 32430 # Number of incorrect RAS predictions.
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 17722520 # DTB read hits
|
|
system.cpu0.dtb.read_misses 56371 # DTB read misses
|
|
system.cpu0.dtb.write_hits 14647463 # DTB write hits
|
|
system.cpu0.dtb.write_misses 8727 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 304 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 2355 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 853 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 17778891 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 14656190 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 32369983 # DTB hits
|
|
system.cpu0.dtb.misses 65098 # DTB misses
|
|
system.cpu0.dtb.accesses 32435081 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.inst_hits 37749886 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 10298 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2364 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 1942 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 37760184 # ITB inst accesses
|
|
system.cpu0.itb.hits 37749886 # DTB hits
|
|
system.cpu0.itb.misses 10298 # DTB misses
|
|
system.cpu0.itb.accesses 37760184 # DTB accesses
|
|
system.cpu0.numCycles 126958641 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 18143411 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 112712815 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 24027935 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 14651504 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 104787507 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 2823240 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 133419 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.MiscStallCycles 39139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingTrapStallCycles 365906 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 432078 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 38034 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 37750510 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 265510 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 3919 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 125351114 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 1.084784 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 1.263056 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 62795131 50.10% 50.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 21461544 17.12% 67.22% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 8765998 6.99% 74.21% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 32328441 25.79% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 125351114 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.189258 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.887792 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 19217150 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 58693987 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 41414238 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 4958351 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 1067388 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 3055751 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 348432 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 110728193 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 3997819 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 1067388 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 24968075 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 11998776 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 36565512 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 40482982 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 10268381 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 105647193 # Number of instructions processed by rename
|
|
system.cpu0.rename.SquashedInsts 1060681 # Number of squashed instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 1440352 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 161094 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LQFullEvents 60996 # Number of times rename has blocked due to LQ full
|
|
system.cpu0.rename.SQFullEvents 6068574 # Number of times rename has blocked due to SQ full
|
|
system.cpu0.rename.RenamedOperands 109731042 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 482381977 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 120921551 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 9385 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 98136808 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 11594231 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 1228692 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 1087401 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 12320869 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 18735521 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 16202725 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 1699910 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 2282844 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 102687285 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 1694390 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 100670059 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 484670 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 9020348 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 22495673 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 122680 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 125351114 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.803105 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.034773 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 69205207 55.21% 55.21% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 23183333 18.49% 73.70% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 22514733 17.96% 91.67% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 9334141 7.45% 99.11% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 1113663 0.89% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 125351114 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 9379501 40.75% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 82 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 5582636 24.26% 65.01% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 8053143 34.99% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 66409608 65.97% 65.97% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 93111 0.09% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.06% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 66.07% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 18430675 18.31% 84.38% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 15726281 15.62% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 100670059 # Type of FU issued
|
|
system.cpu0.iq.rate 0.792936 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 23015362 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.228622 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 350159403 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 113409879 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 98581657 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 31861 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 9722 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 123662544 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 20604 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 365489 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 2006423 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 2595 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 19219 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 1022338 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 106441 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 337136 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 1615648 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 188928 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 104556414 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 18735521 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 16202725 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 876047 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 27263 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 138025 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 19219 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 291871 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 400586 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 692457 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 99572602 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 17974009 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 1032494 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 174739 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 33508875 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 16843329 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 15534866 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.784292 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 99041613 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 98591379 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 51320038 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 84796920 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 0.776563 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.605211 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 8526320 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 1571710 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 633199 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 123596989 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.768069 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.480980 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 79268840 64.13% 64.13% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 24713999 20.00% 84.13% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 8247824 6.67% 90.80% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 3215855 2.60% 93.41% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 3439875 2.78% 96.19% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 1518279 1.23% 97.42% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 1140929 0.92% 98.34% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 533748 0.43% 98.77% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 1517640 1.23% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 123596989 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 78900966 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 94931037 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 31909485 # Number of memory references committed
|
|
system.cpu0.commit.loads 16729098 # Number of loads committed
|
|
system.cpu0.commit.membars 647159 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 16205509 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 81880566 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 1929583 # Number of function calls committed.
|
|
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntAlu 62922752 66.28% 66.28% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntMult 90691 0.10% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 66.39% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemRead 16729098 17.62% 84.01% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemWrite 15180387 15.99% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::total 94931037 # Class of committed instruction
|
|
system.cpu0.commit.bw_lim_events 1517640 # number cycles where commit BW limit reached
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu0.rob.rob_reads 221353668 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 208668086 # The number of ROB writes
|
|
system.cpu0.timesIdled 109562 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 1607527 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 5521753720 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 78778915 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 94808986 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.cpi 1.611581 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 1.611581 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.620508 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.620508 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 110614815 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 59737885 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 8165 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes
|
|
system.cpu0.cc_regfile_reads 350771001 # number of cc regfile reads
|
|
system.cpu0.cc_regfile_writes 41073809 # number of cc regfile writes
|
|
system.cpu0.misc_regfile_reads 245697526 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 1224542 # number of misc regfile writes
|
|
system.cpu0.toL2Bus.trans_dist::ReadReq 2022292 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadResp 1921231 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteReq 19109 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteResp 19109 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::Writeback 512497 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::HardPFReq 635775 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeReq 81120 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43298 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeResp 105236 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExReq 291864 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExResp 281152 # Transaction distribution
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2535030 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2361050 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28910 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120430 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count::total 5045420 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80976096 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86183658 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 218780 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size::total 167428766 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.snoops 1029243 # Total snoops (count)
|
|
system.cpu0.toL2Bus.snoop_fanout::samples 3600041 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::mean 5.252406 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::stdev 0.434393 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::5 2691370 74.76% 74.76% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::6 908671 25.24% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::total 3600041 # Request fanout histogram
|
|
system.cpu0.toL2Bus.reqLayer0.occupancy 1889888022 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.snoopLayer0.occupancy 117489749 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.respLayer0.occupancy 1901826585 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.respLayer1.occupancy 1220473591 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.respLayer2.occupancy 16363478 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.respLayer3.occupancy 65772430 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.icache.tags.replacements 1263981 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.774384 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 36445999 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 1264493 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 28.822618 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 6310719000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774384 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 76759130 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 76759130 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 36445999 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 36445999 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 36445999 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 36445999 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 36445999 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 36445999 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 1301304 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1301304 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 1301304 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1301304 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 1301304 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1301304 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11020664802 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 11020664802 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 11020664802 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 11020664802 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 11020664802 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 11020664802 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 37747303 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 37747303 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 37747303 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 37747303 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 37747303 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 37747303 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034474 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.034474 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034474 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.034474 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034474 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.034474 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8468.939465 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 8468.939465 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8468.939465 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 8468.939465 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8468.939465 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 8468.939465 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 725662 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 84 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 96193 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.543813 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36779 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 36779 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 36779 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 36779 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 36779 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 36779 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264525 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 1264525 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264525 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 1264525 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264525 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 1264525 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8921757516 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 8921757516 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8921757516 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 8921757516 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8921757516 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 8921757516 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243776998 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 243776998 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 243776998 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 243776998 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033500 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.033500 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.033500 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7055.422009 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 7055.422009 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 7055.422009 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11570902 # number of hwpf identified
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 525454 # number of hwpf that were already in mshr
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10431616 # number of hwpf that were already in the cache
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 117790 # number of hwpf that were already in the prefetch queue
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25307 # number of hwpf removed because MSHR allocated
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 470730 # number of hwpf issued
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881250 # number of hwpf spanning a virtual page
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu0.l2cache.tags.replacements 397283 # number of replacements
|
|
system.cpu0.l2cache.tags.tagsinuse 16205.229139 # Cycle average of tags in use
|
|
system.cpu0.l2cache.tags.total_refs 2244912 # Total number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.sampled_refs 413530 # Sample count of references to valid blocks.
|
|
system.cpu0.l2cache.tags.avg_refs 5.428656 # Average number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.warmup_cycle 2809069613500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.l2cache.tags.occ_blocks::writebacks 4639.805304 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.151524 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.649414 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 948.692737 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1410.057987 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9191.872173 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_percent::writebacks 0.283191 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000803 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000101 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.057904 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086063 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.561027 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::total 0.989089 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8152 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8085 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 51 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 237 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3322 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4084 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 458 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 501 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3682 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3594 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 245 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.497559 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.493469 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.tag_accesses 43590224 # Number of tag accesses
|
|
system.cpu0.l2cache.tags.data_accesses 43590224 # Number of data accesses
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54156 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12330 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242747 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.data 407291 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::total 1716524 # number of ReadReq hits
|
|
system.cpu0.l2cache.Writeback_hits::writebacks 512497 # number of Writeback hits
|
|
system.cpu0.l2cache.Writeback_hits::total 512497 # number of Writeback hits
|
|
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15462 # number of UpgradeReq hits
|
|
system.cpu0.l2cache.UpgradeReq_hits::total 15462 # number of UpgradeReq hits
|
|
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2188 # number of SCUpgradeReq hits
|
|
system.cpu0.l2cache.SCUpgradeReq_hits::total 2188 # number of SCUpgradeReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216542 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::total 216542 # number of ReadExReq hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54156 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12330 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.inst 1242747 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.data 623833 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::total 1933066 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54156 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12330 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.inst 1242747 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.data 623833 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::total 1933066 # number of overall hits
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 539 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 228 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21755 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.data 91027 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::total 113549 # number of ReadReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27999 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::total 27999 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18512 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::total 18512 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52925 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::total 52925 # number of ReadExReq misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 539 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 228 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.inst 21755 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.data 143952 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::total 166474 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 539 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 228 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.inst 21755 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.data 143952 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::total 166474 # number of overall misses
|
|
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14141500 # number of ReadReq miss cycles
|
|
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5255000 # number of ReadReq miss cycles
|
|
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 812129434 # number of ReadReq miss cycles
|
|
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2705700107 # number of ReadReq miss cycles
|
|
system.cpu0.l2cache.ReadReq_miss_latency::total 3537226041 # number of ReadReq miss cycles
|
|
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502587457 # number of UpgradeReq miss cycles
|
|
system.cpu0.l2cache.UpgradeReq_miss_latency::total 502587457 # number of UpgradeReq miss cycles
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362338282 # number of SCUpgradeReq miss cycles
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362338282 # number of SCUpgradeReq miss cycles
|
|
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 217500 # number of SCUpgradeFailReq miss cycles
|
|
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 217500 # number of SCUpgradeFailReq miss cycles
|
|
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2594310029 # number of ReadExReq miss cycles
|
|
system.cpu0.l2cache.ReadExReq_miss_latency::total 2594310029 # number of ReadExReq miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14141500 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5255000 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 812129434 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::cpu0.data 5300010136 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::total 6131536070 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14141500 # number of overall miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5255000 # number of overall miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 812129434 # number of overall miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::cpu0.data 5300010136 # number of overall miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::total 6131536070 # number of overall miss cycles
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 54695 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12558 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1264502 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498318 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::total 1830073 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.Writeback_accesses::writebacks 512497 # number of Writeback accesses(hits+misses)
|
|
system.cpu0.l2cache.Writeback_accesses::total 512497 # number of Writeback accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43461 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::total 43461 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20700 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::total 20700 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269467 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::total 269467 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 54695 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12558 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.inst 1264502 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.data 767785 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::total 2099540 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 54695 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12558 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.inst 1264502 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.data 767785 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::total 2099540 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.018156 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017204 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182668 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::total 0.062046 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.644233 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.644233 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.894300 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.894300 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.196406 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.196406 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.018156 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017204 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.187490 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::total 0.079291 # miss rate for demand accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.018156 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017204 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.187490 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::total 0.079291 # miss rate for overall accesses
|
|
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average ReadReq miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23048.245614 # average ReadReq miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37330.702551 # average ReadReq miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29724.148956 # average ReadReq miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31151.538464 # average ReadReq miss latency
|
|
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17950.193114 # average UpgradeReq miss latency
|
|
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17950.193114 # average UpgradeReq miss latency
|
|
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19573.156979 # average SCUpgradeReq miss latency
|
|
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19573.156979 # average SCUpgradeReq miss latency
|
|
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
|
|
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
|
|
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49018.611790 # average ReadExReq miss latency
|
|
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49018.611790 # average ReadExReq miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average overall miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23048.245614 # average overall miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37330.702551 # average overall miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36817.898577 # average overall miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::total 36831.793974 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23048.245614 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37330.702551 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36817.898577 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::total 36831.793974 # average overall miss latency
|
|
system.cpu0.l2cache.blocked_cycles::no_mshrs 59871 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_mshrs 1464 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 40.895492 # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.l2cache.writebacks::writebacks 212118 # number of writebacks
|
|
system.cpu0.l2cache.writebacks::total 212118 # number of writebacks
|
|
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
|
|
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
|
|
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 5582 # number of ReadReq MSHR hits
|
|
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3121 # number of ReadReq MSHR hits
|
|
system.cpu0.l2cache.ReadReq_mshr_hits::total 8705 # number of ReadReq MSHR hits
|
|
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8957 # number of ReadExReq MSHR hits
|
|
system.cpu0.l2cache.ReadExReq_mshr_hits::total 8957 # number of ReadExReq MSHR hits
|
|
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
|
|
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits
|
|
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5582 # number of demand (read+write) MSHR hits
|
|
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 12078 # number of demand (read+write) MSHR hits
|
|
system.cpu0.l2cache.demand_mshr_hits::total 17662 # number of demand (read+write) MSHR hits
|
|
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
|
|
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits
|
|
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 5582 # number of overall MSHR hits
|
|
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 12078 # number of overall MSHR hits
|
|
system.cpu0.l2cache.overall_mshr_hits::total 17662 # number of overall MSHR hits
|
|
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 538 # number of ReadReq MSHR misses
|
|
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 227 # number of ReadReq MSHR misses
|
|
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16173 # number of ReadReq MSHR misses
|
|
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 87906 # number of ReadReq MSHR misses
|
|
system.cpu0.l2cache.ReadReq_mshr_misses::total 104844 # number of ReadReq MSHR misses
|
|
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 470726 # number of HardPFReq MSHR misses
|
|
system.cpu0.l2cache.HardPFReq_mshr_misses::total 470726 # number of HardPFReq MSHR misses
|
|
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27999 # number of UpgradeReq MSHR misses
|
|
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27999 # number of UpgradeReq MSHR misses
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18512 # number of SCUpgradeReq MSHR misses
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18512 # number of SCUpgradeReq MSHR misses
|
|
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43968 # number of ReadExReq MSHR misses
|
|
system.cpu0.l2cache.ReadExReq_mshr_misses::total 43968 # number of ReadExReq MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 538 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 227 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16173 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131874 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::total 148812 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 538 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 227 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16173 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131874 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 470726 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::total 619538 # number of overall MSHR misses
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3653000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 584863774 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2018675176 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2617551450 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21918972757 # number of HardPFReq MSHR miss cycles
|
|
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21918972757 # number of HardPFReq MSHR miss cycles
|
|
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 483477329 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 483477329 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 250147229 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 250147229 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 175500 # number of SCUpgradeFailReq MSHR miss cycles
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 175500 # number of SCUpgradeFailReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1315007380 # number of ReadExReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1315007380 # number of ReadExReq MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3653000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 584863774 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3333682556 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::total 3932558830 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3653000 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 584863774 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3333682556 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21918972757 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::total 25851531587 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218357500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053329974 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4271687474 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040369451 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040369451 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218357500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7093699425 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312056925 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.176405 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057290 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.644233 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.644233 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.894300 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.894300 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163167 # mshr miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163167 # mshr miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171759 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070878 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171759 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.295083 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average ReadReq mshr miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average ReadReq mshr miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average ReadReq mshr miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22964.020385 # average ReadReq mshr miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24966.154000 # average ReadReq mshr miss latency
|
|
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46564.185443 # average HardPFReq mshr miss latency
|
|
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46564.185443 # average HardPFReq mshr miss latency
|
|
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17267.664167 # average UpgradeReq mshr miss latency
|
|
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17267.664167 # average UpgradeReq mshr miss latency
|
|
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13512.706839 # average SCUpgradeReq mshr miss latency
|
|
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13512.706839 # average SCUpgradeReq mshr miss latency
|
|
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
|
|
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
|
|
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29908.282842 # average ReadExReq mshr miss latency
|
|
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29908.282842 # average ReadExReq mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average overall mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average overall mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average overall mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25279.301121 # average overall mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26426.355603 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25279.301121 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46564.185443 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41727.112117 # average overall mshr miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.tags.replacements 712949 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 494.466444 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 28841621 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 713461 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 40.424944 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 256469000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.466444 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965755 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.965755 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 63482821 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 63482821 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 15588564 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 15588564 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 12071351 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 12071351 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311001 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 311001 # number of SoftPFReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363214 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 363214 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360561 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 360561 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 27659915 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 27659915 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 27970916 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 27970916 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 638335 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 638335 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1832649 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1832649 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146162 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 146162 # number of SoftPFReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24977 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 24977 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20700 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 20700 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 2470984 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 2470984 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 2617146 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 2617146 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8102181310 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 8102181310 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25003432618 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 25003432618 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 396859499 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 396859499 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 455692776 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 455692776 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 235500 # number of StoreCondFailReq miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 235500 # number of StoreCondFailReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 33105613928 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 33105613928 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 33105613928 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 33105613928 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 16226899 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 16226899 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904000 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 13904000 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457163 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 457163 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388191 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 388191 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381261 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 381261 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 30130899 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 30130899 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 30588062 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 30588062 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039338 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.039338 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131807 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.131807 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319715 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319715 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064342 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064342 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054294 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054294 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082008 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.082008 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085561 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.085561 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12692.679095 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12692.679095 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13643.328656 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 13643.328656 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15888.997838 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15888.997838 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22014.143768 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22014.143768 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13397.745161 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 13397.745161 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12649.509782 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 12649.509782 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 1233 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 3385599 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 70 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 191316 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.614286 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 17.696371 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 512498 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 512498 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248017 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 248017 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519903 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1519903 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18417 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18417 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767920 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 1767920 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767920 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 1767920 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390318 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 390318 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312746 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 312746 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101547 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 101547 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6560 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6560 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20700 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 20700 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 703064 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 703064 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 804611 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 804611 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4171307993 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4171307993 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4996022111 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4996022111 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1423316745 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1423316745 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98363500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98363500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 413570224 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 413570224 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 223500 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 223500 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9167330104 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 9167330104 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10590646849 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 10590646849 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4216535499 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4216535499 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187175989 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187175989 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7403711488 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7403711488 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024054 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024054 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022493 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022493 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222124 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222124 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016899 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016899 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054294 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054294 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023334 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023334 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026305 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026305 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10686.947548 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10686.947548 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15974.695475 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15974.695475 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14016.334751 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14016.334751 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14994.435976 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14994.435976 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19979.237874 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19979.237874 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13039.111808 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13039.111808 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13162.443527 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13162.443527 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.branchPred.lookups 33913093 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 11564399 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 305039 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 18757536 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 14959019 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 79.749382 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 12491385 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 7180 # Number of incorrect RAS predictions.
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 10162981 # DTB read hits
|
|
system.cpu1.dtb.read_misses 18754 # DTB read misses
|
|
system.cpu1.dtb.write_hits 6542585 # DTB write hits
|
|
system.cpu1.dtb.write_misses 2848 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 49 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 375 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 394 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 10181735 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 6545433 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 16705566 # DTB hits
|
|
system.cpu1.dtb.misses 21602 # DTB misses
|
|
system.cpu1.dtb.accesses 16727168 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.inst_hits 43643100 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 6996 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 1201 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 544 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 43650096 # ITB inst accesses
|
|
system.cpu1.itb.hits 43643100 # DTB hits
|
|
system.cpu1.itb.misses 6996 # DTB misses
|
|
system.cpu1.itb.accesses 43650096 # DTB accesses
|
|
system.cpu1.numCycles 104633766 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 9986103 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 109171918 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 33913093 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 27450404 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 91805384 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 3775592 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.TlbCycles 78970 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu1.fetch.MiscStallCycles 32292 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingTrapStallCycles 198987 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 295254 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 7461 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 43642483 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 116201 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.ItlbSquashes 2279 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 104292247 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 1.296794 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 1.339797 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 47342099 45.39% 45.39% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 14034599 13.46% 58.85% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 7535653 7.23% 66.08% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 35379896 33.92% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 104292247 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.324112 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 1.043372 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 13023476 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 61678123 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 26726804 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 1110708 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 1753136 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 754254 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 137537 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 68065454 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 1169726 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 1753136 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 17456234 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 2244493 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 56986986 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 23381097 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 2470301 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 55158602 # Number of instructions processed by rename
|
|
system.cpu1.rename.SquashedInsts 230731 # Number of squashed instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 262273 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 35381 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LQFullEvents 18008 # Number of times rename has blocked due to LQ full
|
|
system.cpu1.rename.SQFullEvents 1443637 # Number of times rename has blocked due to SQ full
|
|
system.cpu1.rename.RenamedOperands 54999686 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 260535269 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 58684549 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 1692 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 52221656 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 2778030 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 1878103 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 1805469 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 13100518 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 10455886 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 6917101 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 629442 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 825387 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 54265513 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 589015 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 53909819 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 113491 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 2298739 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 5813202 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 48820 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 104292247 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.516911 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 0.852558 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 71040936 68.12% 68.12% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 16527616 15.85% 83.96% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 13076642 12.54% 96.50% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 3359306 3.22% 99.72% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 287734 0.28% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 13 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 104292247 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 2924694 45.09% 45.09% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 678 0.01% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.10% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 1673523 25.80% 70.90% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 1887909 29.10% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 36727877 68.13% 68.13% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 46567 0.09% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 10379543 19.25% 87.47% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 6752424 12.53% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 53909819 # Type of FU issued
|
|
system.cpu1.iq.rate 0.515224 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 6486804 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.120327 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 218706402 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 57161340 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 51920676 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 5778 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 2054 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 60392866 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 3691 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 91423 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 489842 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 678 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 10158 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 359303 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 51794 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 70407 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 1753136 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 542605 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 110606 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 54906673 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 10455886 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 6917101 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 301543 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 9870 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 93230 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 10158 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 54900 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 127108 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 182008 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 53638957 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 10277477 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 249277 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 52145 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 16965020 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 11808497 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 6687543 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.512635 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 53498311 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 51922462 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 25227303 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 38487680 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 0.496230 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.655464 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 3659313 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 540195 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 170379 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 102361190 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.498018 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.158864 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 76777637 75.01% 75.01% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 14293980 13.96% 88.97% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 6079057 5.94% 94.91% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 703860 0.69% 95.60% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 1980599 1.93% 97.53% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 1570719 1.53% 99.07% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 440748 0.43% 99.50% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 123191 0.12% 99.62% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 391399 0.38% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 102361190 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 41391892 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 50977682 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 16523842 # Number of memory references committed
|
|
system.cpu1.commit.loads 9966044 # Number of loads committed
|
|
system.cpu1.commit.membars 209647 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 11639863 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 45828051 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 3366801 # Number of function calls committed.
|
|
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntAlu 34404842 67.49% 67.49% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntMult 45659 0.09% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.58% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemRead 9966044 19.55% 87.14% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemWrite 6557798 12.86% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::total 50977682 # Class of committed instruction
|
|
system.cpu1.commit.bw_lim_events 391399 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.rob.rob_reads 136568898 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 111201426 # The number of ROB writes
|
|
system.cpu1.timesIdled 53211 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 341519 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 5543537240 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 41359038 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 50944828 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.cpi 2.529889 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 2.529889 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.395274 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.395274 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 56284416 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 35740317 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 520 # number of floating regfile writes
|
|
system.cpu1.cc_regfile_reads 191161573 # number of cc regfile reads
|
|
system.cpu1.cc_regfile_writes 15561298 # number of cc regfile writes
|
|
system.cpu1.misc_regfile_reads 205957562 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 388863 # number of misc regfile writes
|
|
system.cpu1.toL2Bus.trans_dist::ReadReq 1295443 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadResp 865390 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteReq 11872 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteResp 11872 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::Writeback 116918 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::HardPFReq 158167 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeReq 84977 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41950 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeResp 87258 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExReq 79543 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExResp 66388 # Transaction distribution
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215693 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825104 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17440 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38012 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count::total 2096249 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25415568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31072 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size::total 64411288 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.snoops 836156 # Total snoops (count)
|
|
system.cpu1.toL2Bus.snoop_fanout::samples 1798706 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::mean 5.418986 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::stdev 0.493393 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::5 1045073 58.10% 58.10% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::6 753633 41.90% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::total 1798706 # Request fanout histogram
|
|
system.cpu1.toL2Bus.reqLayer0.occupancy 658940429 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.snoopLayer0.occupancy 81408998 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.respLayer0.occupancy 913008604 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.respLayer1.occupancy 404124267 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.respLayer2.occupancy 9811221 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.respLayer3.occupancy 21199862 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.icache.tags.replacements 607230 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 499.524831 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 43017967 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 607742 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 70.783272 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 78622263500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524831 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975634 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.975634 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 87892389 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 87892389 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 43017967 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 43017967 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 43017967 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 43017967 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 43017967 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 43017967 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 624354 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 624354 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 624354 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 624354 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 624354 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 624354 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5095463294 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 5095463294 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 5095463294 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 5095463294 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 5095463294 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 5095463294 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 43642321 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 43642321 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 43642321 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 43642321 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 43642321 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 43642321 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014306 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.014306 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014306 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.014306 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014306 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.014306 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8161.176663 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 8161.176663 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8161.176663 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 8161.176663 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8161.176663 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 8161.176663 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 277985 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 36153 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.689127 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16607 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 16607 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 16607 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 16607 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 16607 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 16607 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607747 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 607747 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 607747 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 607747 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 607747 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 607747 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4104727229 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4104727229 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4104727229 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 4104727229 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4104727229 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 4104727229 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7919750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7919750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7919750 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::total 7919750 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6754.006567 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 6754.006567 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 6754.006567 # average overall mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841798 # number of hwpf identified
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 42982 # number of hwpf that were already in mshr
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4639721 # number of hwpf that were already in the cache
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 43013 # number of hwpf that were already in the prefetch queue
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6040 # number of hwpf removed because MSHR allocated
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 110042 # number of hwpf issued
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564522 # number of hwpf spanning a virtual page
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu1.l2cache.tags.replacements 85604 # number of replacements
|
|
system.cpu1.l2cache.tags.tagsinuse 15613.661542 # Cycle average of tags in use
|
|
system.cpu1.l2cache.tags.total_refs 844840 # Total number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.sampled_refs 100686 # Sample count of references to valid blocks.
|
|
system.cpu1.l2cache.tags.avg_refs 8.390839 # Average number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.l2cache.tags.occ_blocks::writebacks 5991.162043 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.384982 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.931077 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 706.431382 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1962.742096 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6937.009962 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_percent::writebacks 0.365672 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000878 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000118 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.043117 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.119796 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.423401 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::total 0.952982 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9479 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5582 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 323 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8003 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1153 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4223 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 941 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.578552 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001282 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.340698 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.tag_accesses 16875679 # Number of tag accesses
|
|
system.cpu1.l2cache.tags.data_accesses 16875679 # Number of data accesses
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16408 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7497 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601881 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.data 101311 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::total 727097 # number of ReadReq hits
|
|
system.cpu1.l2cache.Writeback_hits::writebacks 116917 # number of Writeback hits
|
|
system.cpu1.l2cache.Writeback_hits::total 116917 # number of Writeback hits
|
|
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2261 # number of UpgradeReq hits
|
|
system.cpu1.l2cache.UpgradeReq_hits::total 2261 # number of UpgradeReq hits
|
|
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 836 # number of SCUpgradeReq hits
|
|
system.cpu1.l2cache.SCUpgradeReq_hits::total 836 # number of SCUpgradeReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28901 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::total 28901 # number of ReadExReq hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16408 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7497 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.inst 601881 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.data 130212 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::total 755998 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16408 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7497 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.inst 601881 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.data 130212 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::total 755998 # number of overall hits
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 474 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5861 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.data 72219 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::total 78825 # number of ReadReq misses
|
|
system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
|
|
system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28423 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::total 28423 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22608 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::total 22608 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32938 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::total 32938 # number of ReadExReq misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 474 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.inst 5861 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.data 105157 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::total 111763 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 474 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.inst 5861 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.data 105157 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::total 111763 # number of overall misses
|
|
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10500499 # number of ReadReq miss cycles
|
|
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5483500 # number of ReadReq miss cycles
|
|
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 182847956 # number of ReadReq miss cycles
|
|
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1610079123 # number of ReadReq miss cycles
|
|
system.cpu1.l2cache.ReadReq_miss_latency::total 1808911078 # number of ReadReq miss cycles
|
|
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536990378 # number of UpgradeReq miss cycles
|
|
system.cpu1.l2cache.UpgradeReq_miss_latency::total 536990378 # number of UpgradeReq miss cycles
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 443102047 # number of SCUpgradeReq miss cycles
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 443102047 # number of SCUpgradeReq miss cycles
|
|
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 554000 # number of SCUpgradeFailReq miss cycles
|
|
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 554000 # number of SCUpgradeFailReq miss cycles
|
|
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1287438029 # number of ReadExReq miss cycles
|
|
system.cpu1.l2cache.ReadExReq_miss_latency::total 1287438029 # number of ReadExReq miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10500499 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5483500 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 182847956 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::cpu1.data 2897517152 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::total 3096349107 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10500499 # number of overall miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5483500 # number of overall miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 182847956 # number of overall miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::cpu1.data 2897517152 # number of overall miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::total 3096349107 # number of overall miss cycles
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16882 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7768 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607742 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173530 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::total 805922 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.Writeback_accesses::writebacks 116918 # number of Writeback accesses(hits+misses)
|
|
system.cpu1.l2cache.Writeback_accesses::total 116918 # number of Writeback accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30684 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::total 30684 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23444 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23444 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61839 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::total 61839 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16882 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7768 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.inst 607742 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.data 235369 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::total 867761 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16882 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7768 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.inst 607742 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.data 235369 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::total 867761 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.034887 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009644 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.416176 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::total 0.097807 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000009 # miss rate for Writeback accesses
|
|
system.cpu1.l2cache.Writeback_miss_rate::total 0.000009 # miss rate for Writeback accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926313 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926313 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.964341 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.964341 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532641 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532641 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.034887 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009644 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446775 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::total 0.128795 # miss rate for demand accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.034887 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009644 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446775 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::total 0.128795 # miss rate for overall accesses
|
|
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average ReadReq miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20234.317343 # average ReadReq miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31197.399079 # average ReadReq miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22294.397915 # average ReadReq miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22948.443742 # average ReadReq miss latency
|
|
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18892.811385 # average UpgradeReq miss latency
|
|
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18892.811385 # average UpgradeReq miss latency
|
|
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19599.347443 # average SCUpgradeReq miss latency
|
|
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19599.347443 # average SCUpgradeReq miss latency
|
|
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 184666.666667 # average SCUpgradeFailReq miss latency
|
|
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 184666.666667 # average SCUpgradeFailReq miss latency
|
|
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39086.709242 # average ReadExReq miss latency
|
|
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39086.709242 # average ReadExReq miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average overall miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20234.317343 # average overall miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 31197.399079 # average overall miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27554.201356 # average overall miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::total 27704.599080 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20234.317343 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 31197.399079 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27554.201356 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::total 27704.599080 # average overall miss latency
|
|
system.cpu1.l2cache.blocked_cycles::no_mshrs 23432 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_mshrs 464 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 50.500000 # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.l2cache.writebacks::writebacks 40723 # number of writebacks
|
|
system.cpu1.l2cache.writebacks::total 40723 # number of writebacks
|
|
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 14 # number of ReadReq MSHR hits
|
|
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1292 # number of ReadReq MSHR hits
|
|
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 76 # number of ReadReq MSHR hits
|
|
system.cpu1.l2cache.ReadReq_mshr_hits::total 1382 # number of ReadReq MSHR hits
|
|
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1310 # number of ReadExReq MSHR hits
|
|
system.cpu1.l2cache.ReadExReq_mshr_hits::total 1310 # number of ReadExReq MSHR hits
|
|
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 14 # number of demand (read+write) MSHR hits
|
|
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1292 # number of demand (read+write) MSHR hits
|
|
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1386 # number of demand (read+write) MSHR hits
|
|
system.cpu1.l2cache.demand_mshr_hits::total 2692 # number of demand (read+write) MSHR hits
|
|
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 14 # number of overall MSHR hits
|
|
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1292 # number of overall MSHR hits
|
|
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1386 # number of overall MSHR hits
|
|
system.cpu1.l2cache.overall_mshr_hits::total 2692 # number of overall MSHR hits
|
|
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 474 # number of ReadReq MSHR misses
|
|
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 257 # number of ReadReq MSHR misses
|
|
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4569 # number of ReadReq MSHR misses
|
|
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72143 # number of ReadReq MSHR misses
|
|
system.cpu1.l2cache.ReadReq_mshr_misses::total 77443 # number of ReadReq MSHR misses
|
|
system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
|
|
system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
|
|
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 110035 # number of HardPFReq MSHR misses
|
|
system.cpu1.l2cache.HardPFReq_mshr_misses::total 110035 # number of HardPFReq MSHR misses
|
|
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28423 # number of UpgradeReq MSHR misses
|
|
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28423 # number of UpgradeReq MSHR misses
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22608 # number of SCUpgradeReq MSHR misses
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22608 # number of SCUpgradeReq MSHR misses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
|
|
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31628 # number of ReadExReq MSHR misses
|
|
system.cpu1.l2cache.ReadExReq_mshr_misses::total 31628 # number of ReadExReq MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 474 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 257 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4569 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103771 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::total 109071 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 474 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 257 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4569 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103771 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 110035 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::total 219106 # number of overall MSHR misses
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3513000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 126144777 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1103468683 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1240306961 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3485961286 # number of HardPFReq MSHR miss cycles
|
|
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3485961286 # number of HardPFReq MSHR miss cycles
|
|
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 417373575 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 417373575 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308955268 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308955268 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 463000 # number of SCUpgradeFailReq MSHR miss cycles
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 463000 # number of SCUpgradeFailReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 944601401 # number of ReadExReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 944601401 # number of ReadExReq MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3513000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 126144777 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2048070084 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::total 2184908362 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3513000 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 126144777 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2048070084 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3485961286 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::total 5670869648 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7061250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2181994006 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189055256 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737322501 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737322501 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7061250 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919316507 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3926377757 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415738 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.096092 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for Writeback accesses
|
|
system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000009 # mshr miss rate for Writeback accesses
|
|
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926313 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926313 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.964341 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.964341 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
|
|
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.511457 # mshr miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.511457 # mshr miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440886 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125692 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440886 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.252496 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average ReadReq mshr miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average ReadReq mshr miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average ReadReq mshr miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15295.575219 # average ReadReq mshr miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16015.740106 # average ReadReq mshr miss latency
|
|
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31680.476994 # average HardPFReq mshr miss latency
|
|
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31680.476994 # average HardPFReq mshr miss latency
|
|
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14684.360377 # average UpgradeReq mshr miss latency
|
|
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14684.360377 # average UpgradeReq mshr miss latency
|
|
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.749646 # average SCUpgradeReq mshr miss latency
|
|
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.749646 # average SCUpgradeReq mshr miss latency
|
|
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 154333.333333 # average SCUpgradeFailReq mshr miss latency
|
|
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 154333.333333 # average SCUpgradeFailReq mshr miss latency
|
|
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29865.985867 # average ReadExReq mshr miss latency
|
|
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29865.985867 # average ReadExReq mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average overall mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average overall mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average overall mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19736.439699 # average overall mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20031.982488 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19736.439699 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31680.476994 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25881.854664 # average overall mshr miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.tags.replacements 191151 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 472.645791 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 15740842 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 191475 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 82.208341 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 102871069000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.645791 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923136 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.923136 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 32982505 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 32982505 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 9573878 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 9573878 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 5910219 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 5910219 # number of WriteReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49544 # number of SoftPFReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::total 49544 # number of SoftPFReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79107 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 79107 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70933 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 70933 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 15484097 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 15484097 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 15533641 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 15533641 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 219762 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 219762 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 398432 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 398432 # number of WriteReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30092 # number of SoftPFReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::total 30092 # number of SoftPFReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18147 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 18147 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23447 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 23447 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 618194 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 618194 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 648286 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 648286 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3451433990 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 3451433990 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8738929077 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 8738929077 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362617750 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 362617750 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 543339293 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 543339293 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 593000 # number of StoreCondFailReq miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 593000 # number of StoreCondFailReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 12190363067 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 12190363067 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 12190363067 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 12190363067 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793640 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 9793640 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308651 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 6308651 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79636 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::total 79636 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97254 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 97254 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94380 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 94380 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 16102291 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 16102291 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 16181927 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 16181927 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022439 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.022439 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063156 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.063156 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377869 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377869 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186594 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186594 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248432 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248432 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038392 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.038392 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040062 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.040062 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15705.326626 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15705.326626 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21933.301233 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21933.301233 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19982.242244 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19982.242244 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23173.083678 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23173.083678 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19719.316375 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 19719.316375 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18803.989392 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 18803.989392 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 1116254 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 47 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 39673 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.191489 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets 28.136365 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 116918 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 116918 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79804 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 79804 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306588 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 306588 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13195 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13195 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 386392 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 386392 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 386392 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 386392 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139958 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 139958 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91844 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 91844 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28639 # number of SoftPFReq MSHR misses
|
|
system.cpu1.dcache.SoftPFReq_mshr_misses::total 28639 # number of SoftPFReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4952 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4952 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23447 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23447 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 231802 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 231802 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 260441 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 260441 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1829576308 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1829576308 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2203829941 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2203829941 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 493924497 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 493924497 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86545750 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86545750 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 495264707 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 495264707 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 567000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 567000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4033406249 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 4033406249 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4527330746 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 4527330746 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298504494 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298504494 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826458496 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826458496 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4124962990 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4124962990 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014291 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014291 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014558 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014558 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359624 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359624 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050918 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050918 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248432 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248432 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014396 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.014396 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016095 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.016095 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13072.323897 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13072.323897 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23995.361058 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23995.361058 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17246.569259 # average SoftPFReq mshr miss latency
|
|
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17246.569259 # average SoftPFReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17476.928514 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17476.928514 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21122.732418 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21122.732418 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17400.221952 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.221952 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17383.325767 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17383.325767 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.tags.replacements 36453 # number of replacements
|
|
system.iocache.tags.tagsinuse 14.560241 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 254140751000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 14.560241 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.910015 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.910015 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328407 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328407 # Number of data accesses
|
|
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
|
|
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
|
|
system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 247 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::realview.ide 21 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 21 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 247 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 247 # number of overall misses
|
|
system.iocache.overall_misses::total 247 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ide 30846377 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 30846377 # number of ReadReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 30846377 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 30846377 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 30846377 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 30846377 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 36245 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 36245 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000579 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 0.000579 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 124884.117409 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 124884.117409 # average ReadReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 124884.117409 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 124884.117409 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 36224 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 247 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 18001377 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 18001377 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2249753293 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2249753293 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 18001377 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 18001377 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 18001377 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 18001377 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72880.068826 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 72880.068826 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 2758 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|