257 lines
8.9 KiB
C++
257 lines
8.9 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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// Gabe Black
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////////////////////////////////////////////////////////////////////
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//
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// Common microop templates
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//
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def template MicroConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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RegIndex _ura,
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RegIndex _urb,
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uint8_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_ura, _urb, _imm)
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{
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%(constructor)s;
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}
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Load/store microops
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//
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def template MicroMemDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst,
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RegIndex _ura, RegIndex _urb,
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uint8_t _imm);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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let {{
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microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
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'MicroMemOp',
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{'memacc_code': 'Ra = Mem;',
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'ea_code': 'EA = Rb + (UP ? imm : -imm);',
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'predicate_test': predicateTest},
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['IsMicroop'])
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microLdrRetUopCode = '''
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Ra = Mem;
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Cpsr = cpsrWriteByInstr(Cpsr, Spsr, 0xF, true);
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'''
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microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
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'MicroMemOp',
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{'memacc_code': microLdrRetUopCode,
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'ea_code':
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'EA = Rb + (UP ? imm : -imm);',
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'predicate_test': predicateTest},
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['IsMicroop'])
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microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
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'MicroMemOp',
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{'memacc_code': 'Mem = Ra;',
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'ea_code': 'EA = Rb + (UP ? imm : -imm);',
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'predicate_test': predicateTest},
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['IsMicroop'])
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header_output = MicroMemDeclare.subst(microLdrUopIop) + \
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MicroMemDeclare.subst(microLdrRetUopIop) + \
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MicroMemDeclare.subst(microStrUopIop)
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decoder_output = MicroConstructor.subst(microLdrUopIop) + \
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MicroConstructor.subst(microLdrRetUopIop) + \
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MicroConstructor.subst(microStrUopIop)
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exec_output = LoadExecute.subst(microLdrUopIop) + \
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LoadExecute.subst(microLdrRetUopIop) + \
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StoreExecute.subst(microStrUopIop) + \
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LoadInitiateAcc.subst(microLdrUopIop) + \
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LoadInitiateAcc.subst(microLdrRetUopIop) + \
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StoreInitiateAcc.subst(microStrUopIop) + \
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LoadCompleteAcc.subst(microLdrUopIop) + \
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LoadCompleteAcc.subst(microLdrRetUopIop) + \
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StoreCompleteAcc.subst(microStrUopIop)
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Integer = Integer op Immediate microops
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//
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def template MicroIntDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst,
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RegIndex _ura, RegIndex _urb,
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uint8_t _imm);
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%(BasicExecDeclare)s
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};
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}};
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let {{
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microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
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'MicroIntOp',
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{'code': 'Ra = Rb + imm;',
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'predicate_test': predicateTest},
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['IsMicroop'])
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microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
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'MicroIntOp',
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{'code': 'Ra = Rb - imm;',
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'predicate_test': predicateTest},
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['IsMicroop'])
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header_output = MicroIntDeclare.subst(microAddiUopIop) + \
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MicroIntDeclare.subst(microSubiUopIop)
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decoder_output = MicroConstructor.subst(microAddiUopIop) + \
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MicroConstructor.subst(microSubiUopIop)
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exec_output = PredOpExecute.subst(microAddiUopIop) + \
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PredOpExecute.subst(microSubiUopIop)
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Macro Memory-format instructions
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//
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def template MacroStoreDeclare {{
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/**
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* Static instructions class for a store multiple instruction
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*/
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst);
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%(BasicExecDeclare)s
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};
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}};
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def template MacroStoreConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
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{
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%(constructor)s;
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uint32_t regs = reglist;
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uint32_t addr = 0;
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bool up = machInst.puswl.up;
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if (!up)
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addr = (ones << 2) - 4;
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if (machInst.puswl.prepost)
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addr += 4;
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// Add 0 to Rn and stick it in ureg0.
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// This is equivalent to a move.
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microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0);
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unsigned reg = 0;
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bool force_user = machInst.puswl.psruser & !OPCODE_15;
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bool exception_ret = machInst.puswl.psruser & OPCODE_15;
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for (int i = 1; i < ones + 1; i++) {
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// Find the next register.
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while (!bits(regs, reg))
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reg++;
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replaceBits(regs, reg, 0);
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unsigned regIdx = reg;
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if (force_user) {
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regIdx = intRegForceUser(regIdx);
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}
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if (machInst.puswl.loadOp) {
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if (reg == INTREG_PC && exception_ret) {
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// This must be the exception return form of ldm.
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microOps[i] =
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new MicroLdrRetUop(machInst, regIdx, INTREG_UREG0, addr);
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} else {
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microOps[i] =
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new MicroLdrUop(machInst, regIdx, INTREG_UREG0, addr);
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}
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} else {
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microOps[i] =
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new MicroStrUop(machInst, regIdx, INTREG_UREG0, addr);
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}
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if (up)
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addr += 4;
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else
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addr -= 4;
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}
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StaticInstPtr &lastUop = microOps[numMicroops - 1];
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if (machInst.puswl.writeback) {
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if (up) {
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lastUop = new MicroAddiUop(machInst, RN, RN, ones * 4);
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} else {
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lastUop = new MicroSubiUop(machInst, RN, RN, ones * 4);
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}
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}
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lastUop->setLastMicroop();
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}
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}};
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def template MacroStoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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if (fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{
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iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags)
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header_output = MacroStoreDeclare.subst(iop)
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decoder_output = MacroStoreConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = MacroStoreExecute.subst(iop)
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}};
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